mirror of https://github.com/YosysHQ/yosys.git
cb07710162
Processes without sync rules correspond to simple decision trees that directly correspond to `always @*` or `always_comb` blocks in Verilog, and do not need a warning. This removes the need to suppress warnings during the RTLIL-to-Verilog conversion performed by Amaranth. |
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| .. | ||
| aiger | ||
| blif | ||
| btor | ||
| cxxrtl | ||
| edif | ||
| firrtl | ||
| intersynth | ||
| jny | ||
| json | ||
| rtlil | ||
| simplec | ||
| smt2 | ||
| smv | ||
| spice | ||
| table | ||
| verilog | ||