luke
/
yosys
mirror of https://github.com/YosysHQ/yosys.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity
yosys/backends/verilog
History
whitequark 42c47a83da write_verilog: escape names that match SystemVerilog keywords. 2019-01-27 00:03:53 +00:00
..
Makefile.inc initial import 2013-01-05 11:13:26 +01:00
verilog_backend.cc write_verilog: escape names that match SystemVerilog keywords. 2019-01-27 00:03:53 +00:00