yosys/techlibs/rapidflex/alkaidL/cell_sim.v

8 lines
240 B
Verilog

//-------------------------------------------------
// Include all the primitives
//-------------------------------------------------
`include "cell_sim_arith.v"
`include "cell_sim_dsp.v"
`include "cell_sim_bram.v"
`include "cell_sim_ff.v"