Gus Smith e3db8fee6f Merge pull request #3459 from gs-jgj/feature_dsp48e1_presub ...

Add support for subtract in preadder

2026-02-11 08:02:18 -08:00

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tests

Add a general tests/.gitignore and remove redundant entries in subdirectory .gitignore files.

2025-07-22 10:38:38 +00:00

abc9_model.v

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arith_map.v

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brams_defs.vh

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brams_xc2v_map.v

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brams_xc2v.txt

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brams_xc3sda_map.v

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brams_xc3sda.txt

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brams_xc4v_map.v

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brams_xc4v.txt

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brams_xc5v_map.v

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brams_xc6v_map.v

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brams_xcu_map.v

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brams_xcv_map.v

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brams_xcv.txt

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cells_map.v

Clearer diff for the all-x corner case

2025-04-07 07:55:30 +02:00

cells_sim.v

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cells_xtra.py

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cells_xtra.v

Add and use fix_mod.py

2026-01-28 07:45:58 +13:00

ff_map.v

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lut_map.v

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lutrams_xc5v_map.v

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lutrams_xc5v.txt

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lutrams_xcu.txt

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lutrams_xcv_map.v

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lutrams_xcv.txt

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Makefile.inc

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mux_map.v

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synth_xilinx.cc

Move Design::sort() calls out of opt and opt_clean passes into the synth passes that need them.

2026-01-23 01:14:35 +00:00

urams_map.v

URAM mapping : Fix port indexes according to Yosys warnings

2025-05-09 15:09:11 +02:00

urams.txt

URAM mapping : Add test for 2048 x 144b

2025-05-10 14:53:56 +02:00

xc3s_mult_map.v

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xc3sda_dsp_map.v

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xc4v_dsp_map.v

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xc5v_dsp_map.v

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xc6s_dsp_map.v

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xc7_dsp_map.v

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xcu_dsp_map.v

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xilinx_dffopt.cc

Update techlibs to avoid bits()

2025-09-16 03:17:23 +00:00

xilinx_dsp48a.pmg

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xilinx_dsp_cascade.pmg

xilinx: fix IdString memory leak

2025-11-13 14:10:52 +01:00

xilinx_dsp_CREG.pmg

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xilinx_dsp.cc

Add support for subtraction in preadder

2026-02-03 08:31:01 -08:00

xilinx_dsp.pmg

Add support for subtraction in preadder

2026-02-03 08:31:01 -08:00

xilinx_srl.cc

Update techlibs to avoid bits()

2025-09-16 03:17:23 +00:00

xilinx_srl.pmg

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