yosys/frontends at 41b41fefb38900e12e709137a35565cceb0bf02b - yosys - Gitea: Git with a cup of tea

luke/yosys

mirror of https://github.com/YosysHQ/yosys.git synced 2026-09-03 03:13:21 +02:00

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Emil J. Tywoniak ad7a776d73 genrtlil: even faster removeSignalFromCaseTree

2026-03-18 23:33:35 +01:00

..

yosys: use newcelltypes for yosys_celltypes users

2026-03-04 12:39:44 +01:00

Enable xaiger2 pass when not in NDEBUG

2025-11-21 14:23:32 -08:00

genrtlil: even faster removeSignalFromCaseTree

2026-03-18 23:33:35 +01:00

blifparse: add bounds check

2026-02-11 12:16:02 +01:00

Support param. default values in JSON FE and SV BE

2026-02-11 08:10:55 -08:00

read_liberty: support loopy retention cells

2025-11-20 13:21:32 +01:00

Remove .c_str() from parameters to log_debug()

2025-09-23 19:10:33 +12:00

Work around std::reverse miscompilation with empty range

2026-03-06 02:03:21 +00:00

Guard vhdl_file::UNDEFINED behind VERIFIC_VHDL_SUPPORT.

2026-02-02 15:26:03 -08:00

support automatic lifetime qualifier on procedural variables

2026-02-27 20:42:52 +03:00