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mirror of https://github.com/YosysHQ/yosys.git synced 2026-10-06 10:03:36 +02:00
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3fb32540ea3febc43fce25abcd04f42e7e1ec234
yosys/passes
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History
Miodrag Milanovic 3730db4b98 AIM file could have gaps in or between inputs and inits
2022-05-02 11:18:30 +02:00
..
cmds
show: Fix width labels.
2022-04-04 22:48:09 +02:00
equiv
Fixing old e-mail addresses and deadnames
2021-06-08 00:39:36 +02:00
fsm
Fixing old e-mail addresses and deadnames
2021-06-08 00:39:36 +02:00
hierarchy
Reorder steps in -auto-top to fix synth command, fixes #3261
2022-04-05 14:02:37 +02:00
memory
memory_share: Fix up mismatched address widths.
2022-04-15 22:01:00 +02:00
opt
opt_dff: Fix behavior on $ff with D == Q.
2022-04-15 22:00:32 +02:00
pmgen
Update comment
2022-02-02 03:21:09 +01:00
proc
proc_dff: Emit $aldff.
2021-10-27 14:14:24 +02:00
sat
AIM file could have gaps in or between inputs and inits
2022-05-02 11:18:30 +02:00
techmap
tribuf: -formal option: convert all to logic and detect conflicts
2022-04-12 12:46:22 +02:00
tests
Add $bmux and $demux cells.
2022-01-28 23:34:41 +01:00
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