yosys/passes
Robert O'Callahan 3f2c4f6f83 Remove redundant construction of `assign_map`.
We call 'assign_map.set()' below which wipes the `SigMap` and reconstructs it.

This operation is expensive because it scans the whole module. I think it's
better to make heavyweight operations more visible so I'm removing
the less obvious operation.
2025-08-17 23:34:11 +00:00
..
cmds rename: format vector slices consistently with HDL upto/downto direction 2025-08-13 11:11:53 +02:00
equiv equiv_simple: Avoid std::array 2025-08-08 12:37:38 +12:00
fsm
hierarchy Reapply "Add groups to command reference" 2025-08-06 13:52:12 +12:00
memory ast, read_verilog: ownership in AST, use C++ styles for parser and lexer 2025-08-11 13:34:10 +02:00
opt Remove redundant construction of `assign_map`. 2025-08-17 23:34:11 +00:00
pmgen Reapply "Add groups to command reference" 2025-08-06 13:52:12 +12:00
proc Proc: Use selections consistently 2025-05-31 12:04:42 +12:00
sat Reapply "Add groups to command reference" 2025-08-06 13:52:12 +12:00
techmap Build FfInitVals for the entire module once and use it for every ABC run. 2025-08-14 22:29:51 +00:00
tests test_cell: Add comment on $pmux 2025-08-12 10:57:59 +12:00