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luke
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yosys
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3ee33cbdaf7ae8ef85e595fb2266ad92a17cfaeb
yosys
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techlibs
T
History
Clifford Wolf
1afe6589df
Renamed stdcells_sim.v to simcells.v and fixed blackbox.v
2013-11-24 20:44:00 +01:00
..
cmos
Updated abc
2013-11-21 22:39:10 +01:00
common
Renamed stdcells_sim.v to simcells.v and fixed blackbox.v
2013-11-24 20:44:00 +01:00
xilinx
Added "techmap -share_map" option
2013-11-24 19:50:25 +01:00
.gitignore
added .gitignore files
2013-01-05 11:19:11 +01:00