luke/yosys
1
0
Fork 0
mirror of https://github.com/YosysHQ/yosys.git synced 2026-08-29 01:24:25 +02:00
Code Issues Packages Projects Releases Wiki Activity
Files
3ec00cceaa62ad7e06bdaa0fa48eaaffeae8982c
yosys/tests/svinterfaces
T
History
Dag Lem 615adc4253 Resolve package types in interfaces (#3658) 
* Resolve package types in interfaces
* Added test for resolving of package types in interfaces
2023-02-12 18:25:39 -05:00
..
.gitignore
Add missing .gitignore
2018-12-06 07:29:37 +01:00
load_and_derive.sv
Add a test for interfaces on modules loaded on-demand
2021-07-14 22:54:50 -04:00
load_and_derive.ys
Add a test for interfaces on modules loaded on-demand
2021-07-14 22:54:50 -04:00
ondemand.sv
Add a test for interfaces on modules loaded on-demand
2021-07-14 22:54:50 -04:00
resolve_types.sv
Resolve package types in interfaces (#3658)
2023-02-12 18:25:39 -05:00
resolve_types.ys
Resolve package types in interfaces (#3658)
2023-02-12 18:25:39 -05:00
run_simple.sh
Add a test for interfaces on modules loaded on-demand
2021-07-14 22:54:50 -04:00
run-test.sh
Resolve package types in interfaces (#3658)
2023-02-12 18:25:39 -05:00
runone.sh
Fix typo in tests/svinterfaces/runone.sh
2019-05-03 14:40:51 +02:00
svinterface1_ref.v
Basic test for checking correct synthesis of SystemVerilog interfaces
2018-10-18 22:40:53 +02:00
svinterface1_tb.v
Basic test for checking correct synthesis of SystemVerilog interfaces
2018-10-18 22:40:53 +02:00
svinterface1.sv
Basic test for checking correct synthesis of SystemVerilog interfaces
2018-10-18 22:40:53 +02:00
svinterface_at_top_ref.v
Support for SystemVerilog interfaces as a port in the top level module + test case
2018-10-20 11:58:25 +02:00
svinterface_at_top_tb_wrapper.v
Support for SystemVerilog interfaces as a port in the top level module + test case
2018-10-20 11:58:25 +02:00
svinterface_at_top_tb.v
Support for SystemVerilog interfaces as a port in the top level module + test case
2018-10-20 11:58:25 +02:00
svinterface_at_top_wrapper.v
Support for SystemVerilog interfaces as a port in the top level module + test case
2018-10-20 11:58:25 +02:00
svinterface_at_top.sv
Support for SystemVerilog interfaces as a port in the top level module + test case
2018-10-20 11:58:25 +02:00