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mirror of https://github.com/YosysHQ/yosys.git synced 2026-08-29 09:30:28 +02:00
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3ec00cceaa62ad7e06bdaa0fa48eaaffeae8982c
yosys/techlibs/intel_alm/common
T
History
Lofty fb7af093a8 intel_alm: re-enable 8x40-bit M10K support
2023-05-29 06:42:03 +01:00
..
abc9_map.v
…
abc9_model.v
…
abc9_unmap.v
…
alm_map.v
…
alm_sim.v
intel_alm: re-enable carry chains for ABC9
2023-05-25 18:28:10 +01:00
arith_alm_map.v
intel_alm: Fix illegal carry chains
2021-05-15 22:37:06 +01:00
bram_m10k_map.v
intel_alm: re-enable 8x40-bit M10K support
2023-05-29 06:42:03 +01:00
bram_m10k.txt
intel_alm: re-enable 8x40-bit M10K support
2023-05-29 06:42:03 +01:00
bram_m20k_map.v
Fix files with CRLF line endings
2021-06-09 12:16:33 +02:00
bram_m20k.txt
…
dff_map.v
…
dff_sim.v
intel_alm: preliminary Arria V support
2021-11-25 17:20:36 +01:00
dsp_map.v
…
dsp_sim.v
intel_alm: preliminary Arria V support
2021-11-25 17:20:36 +01:00
lutram_mlab.txt
…
megafunction_bb.v
CycloneV: Add (passthrough) support for cyclonev_oscillator
2021-10-17 20:00:03 +02:00
mem_sim.v
intel_alm: enable M10K initialisation
2023-05-25 18:56:34 +01:00
misc_sim.v
intel_alm: Add global buffer insertion
2021-05-15 22:37:06 +01:00
quartus_rename.v
intel_alm: M10K write-enable is negative-true
2022-03-09 20:18:06 +00:00
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