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mirror of https://github.com/YosysHQ/yosys.git synced 2026-08-29 09:30:28 +02:00
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3ec00cceaa62ad7e06bdaa0fa48eaaffeae8982c
yosys/examples/intel/DE2i-150/quartus_compile
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History
Clifford Wolf b72a7e1104 Replace CRLF line endings with LF in de2i.qsf (quartus example)
2017-04-12 16:51:46 +02:00
..
de2i.qpf
Add initial support for both MAX10 and Cyclone IV (E|GX) FPGAs
2017-04-05 23:01:29 -05:00
de2i.qsf
Replace CRLF line endings with LF in de2i.qsf (quartus example)
2017-04-12 16:51:46 +02:00
runme_quartus
Add initial support for both MAX10 and Cyclone IV (E|GX) FPGAs
2017-04-05 23:01:29 -05:00
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