Marcin Kościelnicki 3c75a72feb move attributes to wires

2019-08-13 19:36:59 +00:00

..

achronix

Revert "synth_* with -retime option now calls abc with -D 1 as well"

2019-04-18 07:59:16 -07:00

anlogic

anlogic : Fix alu mapping

2019-08-03 14:47:33 +02:00

common

Reformat so it shows up/looks nice when "help $alu" and "help $alu+"

2019-08-09 12:33:39 -07:00

coolrunner2

Fix spacing

2019-08-06 16:47:55 -07:00

easic

Revert "synth_* with -retime option now calls abc with -D 1 as well"

2019-04-18 07:59:16 -07:00

ecp5

ecp5: Make cells_sim.v consistent with nextpnr

2019-08-07 14:19:31 +01:00

gowin

Fix formatting for msys2 mingw build using GetSize

2019-08-01 17:27:34 +02:00

greenpak4

Revert "synth_* with -retime option now calls abc with -D 1 as well"

2019-04-18 07:59:16 -07:00

ice40

Revert "Wrap SB_LUT+SB_CARRY into $__ICE40_CARRY_WRAPPER"

2019-08-10 17:14:48 +01:00

intel

Merge branch 'ZirconiumX-synth_intel_m9k'

2019-07-25 17:23:48 +02:00

sf2

Revert "synth_* with -retime option now calls abc with -D 1 as well"

2019-04-18 07:59:16 -07:00

xilinx

move attributes to wires

2019-08-13 19:36:59 +00:00

.gitignore

added .gitignore files

2013-01-05 11:19:11 +01:00