This website requires JavaScript.
Explore
Help
Sign In
luke
/
yosys
Watch
1
Star
0
Fork
0
mirror of
https://github.com/YosysHQ/yosys.git
synced
2026-08-30 09:58:22 +02:00
Code
Issues
Packages
Projects
Releases
Wiki
Activity
Files
3a1ef44564de9f7a8e98c1f5dcb6dfd84ffcce1e
yosys
/
techlibs
/
quicklogic
/
common
T
History
N. Engelhardt
98769010af
synth_quicklogic: rearrange files to prepare for adding more architectures
2023-12-04 15:52:02 +01:00
..
cells_sim.v
synth_quicklogic: rearrange files to prepare for adding more architectures
2023-12-04 15:52:02 +01:00