yosys/passes at 3a1ef44564de9f7a8e98c1f5dcb6dfd84ffcce1e - yosys - Gitea: Git with a cup of tea

luke/yosys

mirror of https://github.com/YosysHQ/yosys.git synced 2026-09-02 11:07:41 +02:00

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Martin Povišer fa74d0bd1a check: Use cell edges data in detecting combinational loops

2024-03-11 10:43:49 +01:00

..

check: Use cell edges data in detecting combinational loops

2024-03-11 10:43:49 +01:00

equiv_simple: Take FFs into account for driver map

2024-02-21 12:05:52 +01:00

add option to fsm_detect to ignore self-resetting

2023-01-30 16:12:53 +01:00

hierarchy: Without a known top module, derive all deferred modules

2024-02-06 10:31:40 +01:00

opt_mem, memory_*: Refuse to operate in presence of processes

2024-02-23 12:27:53 +01:00

opt_mem, memory_*: Refuse to operate in presence of processes

2024-02-23 12:27:53 +01:00

Address SigBit/SigSpec confusion issues under c++20

2024-02-08 17:48:36 +01:00

Merge pull request #4218 from kivikakk/proc_rom-actionless-switch

2024-02-19 16:21:40 +01:00

Merge pull request #3972 from nakengelhardt/celledges_shift_ops

2024-03-08 09:35:47 +01:00

Changes in libs, passes and tests Makefiles. LDLIBS -> LIBS. LDFLAGS -> LINKFLAGS. CXX is clang++ or g++, not clang and gcc

2024-02-25 17:23:56 +01:00

Add $bmux and $demux cells.

2022-01-28 23:34:41 +01:00