Logo
Explore Help
Sign In
luke/yosys
Watch 1
Star 0
Fork 0
mirror of https://github.com/YosysHQ/yosys.git synced 2026-09-07 12:21:16 +02:00
Code Issues Packages Projects Releases Wiki Activity
Files
39f4c1096ac3b5964bfa087c2b7f2e8d5a9c1ef3
yosys/frontends
T
History
Eddie Hung 9776084eda Allow whitebox modules to be overwritten
2019-08-07 16:40:24 -07:00
..
aiger
Run "clean" on mapped_mod in its own design
2019-08-07 09:54:27 -07:00
ast
Allow whitebox modules to be overwritten
2019-08-07 16:40:24 -07:00
blif
Add missing "[options]" to read_blif help
2019-02-08 12:41:39 -08:00
ilang
Allow attributes on individual switch cases in RTLIL.
2019-07-08 11:34:58 +00:00
json
Update JSON front-end to process new attr/param encoding
2019-08-01 12:48:22 +02:00
liberty
Fix typo, double "of"
2019-07-16 11:03:30 +02:00
verific
Call "read_verilog" with -defer from "read"
2019-07-29 10:29:36 +02:00
verilog
verilog_lexer: Increase YY_BUF_SIZE to 65536
2019-07-26 13:35:39 +01:00
Powered by Gitea Version: 1.27.2 Page: 173ms Template: 2ms
Auto
English
Bahasa Indonesia Deutsch English Español Français Gaeilge Italiano Latviešu Magyar nyelv Nederlands Polski Português de Portugal Português do Brasil Suomi Svenska Türkçe Čeština Ελληνικά Български Русский Українська فارسی മലയാളം 日本語 简体中文 繁體中文(台灣) 繁體中文(香港) 한국어
Licenses API