mirror of https://github.com/YosysHQ/yosys.git
134 lines
2.1 KiB
Plaintext
134 lines
2.1 KiB
Plaintext
read_verilog <<EOT
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module macc_add3(
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input [7:0] a, b, c,
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output [7:0] y
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);
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assign y = a + b + c;
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endmodule
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EOT
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hierarchy -auto-top
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proc
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alumacc
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opt
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csa_tree
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opt_clean
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select -assert-count 1 t:$fa
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select -assert-count 1 t:$add
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select -assert-none t:$macc t:$macc_v2 %u
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design -reset
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read_verilog <<EOT
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module macc_add4(
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input [7:0] a, b, c, d,
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output [7:0] y
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);
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assign y = a + b + c + d;
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endmodule
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EOT
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hierarchy -auto-top
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proc
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alumacc
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opt
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csa_tree
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opt_clean
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select -assert-count 2 t:$fa
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select -assert-count 1 t:$add
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select -assert-none t:$macc t:$macc_v2 %u
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design -reset
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read_verilog <<EOT
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module macc_add5(
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input [11:0] a, b, c, d, e,
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output [11:0] y
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);
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assign y = a + b + c + d + e;
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endmodule
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EOT
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hierarchy -auto-top
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proc
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alumacc
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opt
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csa_tree
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opt_clean
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select -assert-count 3 t:$fa
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select -assert-count 1 t:$add
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select -assert-none t:$macc t:$macc_v2 %u
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design -reset
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read_verilog <<EOT
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module macc_add8(
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input [15:0] a, b, c, d, e, f, g, h,
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output [15:0] y
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);
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assign y = a + b + c + d + e + f + g + h;
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endmodule
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EOT
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hierarchy -auto-top
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proc
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alumacc
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opt
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csa_tree
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opt_clean
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select -assert-count 6 t:$fa
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select -assert-count 1 t:$add
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select -assert-none t:$macc t:$macc_v2 %u
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design -reset
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read_verilog <<EOT
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module macc_sub_mixed(
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input [7:0] a, b, c, d,
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output [7:0] y
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);
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assign y = a + b - c + d;
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endmodule
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EOT
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hierarchy -auto-top
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proc
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alumacc
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opt
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csa_tree
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opt_clean
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select -assert-none t:$macc t:$macc_v2 %u
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select -assert-min 1 t:$fa
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select -assert-count 1 t:$add
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design -reset
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read_verilog <<EOT
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module macc_const(
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input [7:0] a, b, c,
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output [7:0] y
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);
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assign y = a + b + c + 8'd42;
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endmodule
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EOT
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hierarchy -auto-top
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proc
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alumacc
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opt
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csa_tree
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opt_clean
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select -assert-none t:$macc t:$macc_v2 %u
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select -assert-min 1 t:$fa
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select -assert-count 1 t:$add
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design -reset
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read_verilog <<EOT
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module macc_two(
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input [7:0] a, b, c, d, e, f, g, h,
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output [7:0] y1, y2
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);
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assign y1 = a + b + c + d;
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assign y2 = e + f + g + h;
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endmodule
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EOT
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hierarchy -auto-top
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proc
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alumacc
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opt
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csa_tree
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opt_clean
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select -assert-none t:$macc t:$macc_v2 %u
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select -assert-count 4 t:$fa
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select -assert-count 2 t:$add
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design -reset
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