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mirror of https://github.com/YosysHQ/yosys.git synced 2026-09-01 10:39:10 +02:00
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39759d5f0ec9bfc0db3dd718cb035596da7f9668
yosys/techlibs/gowin
T
History
whitequark 26cda3c247 gowin,ecp5: remove generated files in make clean.
2020-04-24 23:26:39 +00:00
..
.gitignore
gowin: Add missing .gitignore entries
2019-11-22 14:40:36 +01:00
arith_map.v
use ADDSUB ALU mode to remove inverters
2019-10-21 12:00:27 +02:00
brams_init3.vh
GoWin enablement: DRAM, initial BRAM, DRAM init, DRAM sim and synth_gowin flow
2019-04-12 23:40:02 -05:00
brams_init.py
support bram initialisation
2019-09-05 17:25:51 +02:00
brams_map.v
add 32-bit BRAM and byte-enables
2019-10-28 10:33:27 +01:00
brams.txt
Harmonize BRAM/LUTRAM descriptions across all of Yosys.
2020-01-01 12:30:00 +00:00
cells_map.v
attempt to fix formatting
2019-11-25 14:50:34 +01:00
cells_sim.v
add IOBUF
2019-10-28 15:33:05 +01:00
determine_init.cc
kernel: big fat patch to use more ID::*, otherwise ID(*)
2020-04-02 09:51:32 -07:00
lutrams_map.v
Harmonize BRAM/LUTRAM descriptions across all of Yosys.
2020-01-01 12:30:00 +00:00
lutrams.txt
Harmonize BRAM/LUTRAM descriptions across all of Yosys.
2020-01-01 12:30:00 +00:00
Makefile.inc
gowin,ecp5: remove generated files in make clean.
2020-04-24 23:26:39 +00:00
synth_gowin.cc
Get rid of dffsr2dff.
2020-04-15 16:22:37 +02:00
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