Logo
Explore Help
Sign In
luke/yosys
Watch 1
Star 0
Fork 0
mirror of https://github.com/YosysHQ/yosys.git synced 2026-08-29 17:38:17 +02:00
Code Issues Packages Projects Releases Wiki Activity
Files
39759d5f0ec9bfc0db3dd718cb035596da7f9668
yosys/frontends
T
History
Eddie Hung 4017cc6380 aiger: -xaiger to return $_FF_ flops
2020-05-14 10:33:56 -07:00
..
aiger
aiger: -xaiger to return $_FF_ flops
2020-05-14 10:33:56 -07:00
ast
Merge pull request #2027 from YosysHQ/eddie/verilog_neg_upto
2020-05-14 18:06:18 +02:00
blif
kernel: big fat patch to use more ID::*, otherwise ID(*)
2020-04-02 09:51:32 -07:00
ilang
frontend: cleanup to use more ID::*, more dict<> instead of map<>
2020-05-04 10:48:37 -07:00
json
Update JSON front-end to process new attr/param encoding
2019-08-01 12:48:22 +02:00
liberty
kernel: big fat patch to use more ID::*, otherwise ID(*)
2020-04-02 09:51:32 -07:00
rpc
Add WASI platform support.
2020-04-30 18:56:25 +00:00
verific
Add support for non-power-of-two mem chunks in verific importer
2020-05-14 14:38:13 +02:00
verilog
verilog: default to input in sv mode if task/func has no dir ...
2020-05-13 13:33:37 -07:00
Powered by Gitea Version: 1.27.2 Page: 599ms Template: 6ms
Auto
English
Bahasa Indonesia Deutsch English Español Français Gaeilge Italiano Latviešu Magyar nyelv Nederlands Polski Português de Portugal Português do Brasil Suomi Svenska Türkçe Čeština Ελληνικά Български Русский Українська فارسی മലയാളം 日本語 简体中文 繁體中文(台灣) 繁體中文(香港) 한국어
Licenses API