mirror of https://github.com/YosysHQ/yosys.git
117 lines
2.5 KiB
Plaintext
117 lines
2.5 KiB
Plaintext
log -header "Normalize coarse and fine FF/latch polarities"
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log -push
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design -reset
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read_rtlil <<EOT
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module \top
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wire input 1 \clk
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wire input 2 \en
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wire input 3 \arst
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wire input 4 \srst
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wire input 5 \aload
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wire width 2 input 6 \set
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wire width 2 input 7 \clr
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wire width 2 input 8 \d
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wire width 2 input 9 \ad
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wire width 2 output 10 \q_dffe
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wire width 2 output 11 \q_adffe
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wire width 2 output 12 \q_sdffce
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wire width 2 output 13 \q_aldffe
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wire width 2 output 14 \q_dlatchsr
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wire width 2 output 15 \q_sr
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wire output 16 \q_fine
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cell $dffe \dffe_neg
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parameter \CLK_POLARITY 1'0
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parameter \EN_POLARITY 1'0
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parameter \WIDTH 2
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connect \CLK \clk
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connect \EN \en
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connect \D \d
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connect \Q \q_dffe
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end
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cell $adffe \adffe_neg
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parameter \CLK_POLARITY 1'0
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parameter \EN_POLARITY 1'0
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parameter \ARST_POLARITY 1'0
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parameter \ARST_VALUE 2'01
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parameter \WIDTH 2
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connect \CLK \clk
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connect \EN \en
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connect \ARST \arst
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connect \D \d
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connect \Q \q_adffe
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end
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cell $sdffce \sdffce_neg
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parameter \CLK_POLARITY 1'0
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parameter \EN_POLARITY 1'0
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parameter \SRST_POLARITY 1'0
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parameter \SRST_VALUE 2'10
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parameter \WIDTH 2
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connect \CLK \clk
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connect \EN \en
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connect \SRST \srst
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connect \D \d
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connect \Q \q_sdffce
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end
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cell $aldffe \aldffe_neg
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parameter \CLK_POLARITY 1'0
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parameter \EN_POLARITY 1'0
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parameter \ALOAD_POLARITY 1'0
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parameter \WIDTH 2
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connect \CLK \clk
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connect \EN \en
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connect \ALOAD \aload
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connect \D \d
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connect \AD \ad
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connect \Q \q_aldffe
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end
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cell $dlatchsr \dlatchsr_neg
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parameter \EN_POLARITY 1'0
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parameter \SET_POLARITY 1'0
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parameter \CLR_POLARITY 1'0
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parameter \WIDTH 2
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connect \EN \aload
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connect \SET \set
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connect \CLR \clr
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connect \D \d
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connect \Q \q_dlatchsr
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end
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cell $sr \sr_neg
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parameter \SET_POLARITY 1'0
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parameter \CLR_POLARITY 1'0
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parameter \WIDTH 2
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connect \SET \set
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connect \CLR \clr
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connect \Q \q_sr
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end
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cell $_DFFE_NN_ \fine_dffe_neg
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connect \C \clk
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connect \E \en
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connect \D \d [0]
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connect \Q \q_fine
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end
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end
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EOT
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ffnormpol
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check -assert
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select -assert-count 0 r:CLK_POLARITY=0
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select -assert-count 0 r:EN_POLARITY=0
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select -assert-count 0 r:ARST_POLARITY=0
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select -assert-count 0 r:SRST_POLARITY=0
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select -assert-count 0 r:ALOAD_POLARITY=0
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select -assert-count 0 r:SET_POLARITY=0
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select -assert-count 0 r:CLR_POLARITY=0
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select -assert-count 1 t:$_DFFE_PP_
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select -assert-count 7 t:$not
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design -reset
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log -pop
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