Clifford Wolf 361e0d62ff Replaced depricated NEW_WIRE macro with module->addWire() calls

2014-07-21 12:42:02 +02:00

..

bitpattern.h

initial import

2013-01-05 11:13:26 +01:00

calc.cc

Strictly zero-extend unsigned A-inputs of shift operations

2014-03-06 11:53:37 +01:00

celltypes.h

Added support for dlatchsr cells

2014-03-31 14:14:40 +02:00

compatibility.cc

Merged OSX fixes from Siesh1oo with some modifications

2014-03-13 12:48:10 +01:00

compatibility.h

Hotfix for kernel/compatibility.h

2014-03-13 12:55:15 +01:00

consteval.h

Fixed SAT and ConstEval undef handling for $pmux and $safe_pmux

2014-01-03 17:30:50 +01:00

driver.cc

Use "verilog -sv" to parse .sv files

2014-07-11 13:10:51 +02:00

log.cc

Added log_cell()

2014-07-20 10:35:47 +02:00

log.h

Added log_ping()

2014-07-21 12:01:45 +02:00

modwalker.h

Added ModWalker helper class

2014-07-19 15:33:00 +02:00

register.cc

Added call_on_selection() and call_on_module() API

2014-07-20 15:33:06 +02:00

register.h

Added call_on_selection() and call_on_module() API

2014-07-20 15:33:06 +02:00

rtlil.cc

Removed deprecated module->new_wire()

2014-07-21 12:35:06 +02:00

rtlil.h

Replaced depricated NEW_WIRE macro with module->addWire() calls

2014-07-21 12:42:02 +02:00

satgen.h

Bugfix in satgen for cells with wider in- than outputs.

2014-07-21 12:03:41 +02:00

sigtools.h

Some "const" cleanups in SigMap

2014-07-19 15:32:39 +02:00