Miodrag Milanovic 3487b95224 Added simulation models for Efinix and Anlogic

2019-09-15 09:37:16 +02:00

..

arith_map.v

Fix formating

2019-08-11 17:05:24 +02:00

bram.txt

Added bram support

2019-08-04 11:46:36 +02:00

brams_map.v

one bit enable signal

2019-08-11 13:59:39 +02:00

cells_map.v

fix mixing signals on FF mapping

2019-08-11 11:40:15 +02:00

cells_sim.v

Added simulation models for Efinix and Anlogic

2019-09-15 09:37:16 +02:00

efinix_fixcarry.cc

Adding new pass to fix carry chain

2019-08-11 10:17:49 +02:00

efinix_gbuf.cc

clock for ram trough gbuf

2019-08-04 12:17:55 +02:00

Makefile.inc

Fix missing newline at end of file

2019-08-22 18:06:36 +02:00

synth_efinix.cc

Replaced custom step with setundef

2019-08-11 11:01:46 +02:00