Logo
Explore Help
Sign In
luke/yosys
Watch 1
Star 0
Fork 0
mirror of https://github.com/YosysHQ/yosys.git synced 2026-09-01 18:47:29 +02:00
Code Issues Packages Projects Releases Wiki Activity
Files
34572708d5df970d73ca0702584ac161ca4584ae
yosys/techlibs/microchip
T
History
chunlin min 3db69b7a10 inline all tests. Add switch to remove init values as PolarFire DFFs do not support init
2024-07-08 17:03:03 -04:00
..
arith_map.v
add assertions for synth_microchip tests
2024-07-04 15:45:44 -04:00
brams_defs.vh
Add missing u sram init (#3)
2024-07-04 16:39:10 -04:00
cells_map.v
changes made to filenames + references
2024-07-04 08:53:41 -07:00
cells_sim.v
Revisions (#4)
2024-07-08 10:57:16 -04:00
LSRAM_map.v
changes made to filenames + references
2024-07-04 08:53:41 -07:00
LSRAM.txt
changes made to filenames + references
2024-07-04 08:53:41 -07:00
Makefile.inc
fixed typos, build with makefile succeeds
2024-07-04 09:33:58 -07:00
microchip_dffopt.cc
initialize argidx to 1
2024-07-08 11:41:41 -04:00
polarfire_dsp_map.v
changes made to filenames + references
2024-07-04 08:53:41 -07:00
synth_microchip.cc
inline all tests. Add switch to remove init values as PolarFire DFFs do not support init
2024-07-08 17:03:03 -04:00
uSRAM_map.v
Add missing u sram init (#3)
2024-07-04 16:39:10 -04:00
uSRAM.txt
changes made to filenames + references
2024-07-04 08:53:41 -07:00
Powered by Gitea Version: 1.27.2 Page: 447ms Template: 9ms
Auto
English
Bahasa Indonesia Deutsch English Español Français Gaeilge Italiano Latviešu Magyar nyelv Nederlands Polski Português de Portugal Português do Brasil Suomi Svenska Türkçe Čeština Ελληνικά Български Русский Українська فارسی മലയാളം 日本語 简体中文 繁體中文(台灣) 繁體中文(香港) 한국어
Licenses API