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yosys/techlibs/xilinx
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whitequark 7191dd16f9 Use C++11 final/override keywords.
2020-06-18 23:34:52 +00:00
..
tests
xilinx: Add simulation model for DSP48 (Virtex 4).
2020-01-29 01:40:00 +01:00
.gitignore
…
abc9_model.v
abc9_ops: add -prep_bypass for auto bypass boxes; refactor
2020-05-14 10:33:56 -07:00
arith_map.v
Add force_downto and force_upto wire attributes.
2020-05-19 01:42:40 +02:00
brams_init.py
…
cells_map.v
Add force_downto and force_upto wire attributes.
2020-05-19 01:42:40 +02:00
cells_sim.v
xilinx: tidy up cells_sim.v a little
2020-05-25 09:48:11 -07:00
cells_xtra.py
xilinx: Mark IOBUFDS.IOB as external pad
2020-03-20 14:37:38 +01:00
cells_xtra.v
xilinx: Mark IOBUFDS.IOB as external pad
2020-03-20 14:37:38 +01:00
lut4_lutrams.txt
xilinx: Add support for LUT RAM on LUT4-based devices.
2020-02-07 09:03:22 +01:00
lut6_lutrams.txt
xilinx: Add support for LUT RAM on LUT4-based devices.
2020-02-07 09:03:22 +01:00
lut_map.v
Add force_downto and force_upto wire attributes.
2020-05-19 01:42:40 +02:00
lutrams_map.v
…
Makefile.inc
abc9_ops: add -prep_bypass for auto bypass boxes; refactor
2020-05-14 10:33:56 -07:00
mux_map.v
Add force_downto and force_upto wire attributes.
2020-05-19 01:42:40 +02:00
synth_xilinx.cc
Use C++11 final/override keywords.
2020-06-18 23:34:52 +00:00
xc2v_brams_map.v
xilinx: Add block RAM mapping for Virtex 2* and Spartan 3*.
2020-02-07 01:00:29 +01:00
xc2v_brams.txt
xilinx: Add block RAM mapping for Virtex 2* and Spartan 3*.
2020-02-07 01:00:29 +01:00
xc3s_mult_map.v
…
xc3sa_brams.txt
xilinx: Add block RAM mapping for Virtex 2* and Spartan 3*.
2020-02-07 01:00:29 +01:00
xc3sda_brams.txt
xilinx: Add block RAM mapping for Virtex 2* and Spartan 3*.
2020-02-07 01:00:29 +01:00
xc3sda_dsp_map.v
…
xc4v_dsp_map.v
…
xc5v_dsp_map.v
…
xc6s_brams_map.v
xilinx: Add block RAM mapping for Virtex 2* and Spartan 3*.
2020-02-07 01:00:29 +01:00
xc6s_brams.txt
xilinx: Add block RAM mapping for Virtex 2* and Spartan 3*.
2020-02-07 01:00:29 +01:00
xc6s_dsp_map.v
…
xc6s_ff_map.v
…
xc7_brams_map.v
xilinx: Add block RAM mapping for Virtex 2* and Spartan 3*.
2020-02-07 01:00:29 +01:00
xc7_dsp_map.v
…
xc7_ff_map.v
…
xc7_xcu_brams.txt
xilinx: Add block RAM mapping for Virtex 2* and Spartan 3*.
2020-02-07 01:00:29 +01:00
xcu_brams_map.v
xilinx: Add block RAM mapping for Virtex 2* and Spartan 3*.
2020-02-07 01:00:29 +01:00
xcu_dsp_map.v
…
xcup_urams_map.v
…
xcup_urams.txt
…
xilinx_dffopt.cc
Use C++11 final/override keywords.
2020-06-18 23:34:52 +00:00