Clifford Wolf 57fc8dd582 Add "synth_ice40 -json" ...

Signed-off-by: Clifford Wolf <[email protected]>

2018-06-13 13:35:10 +02:00

..

tests

Initialization support for all iCE40 bram modes

2015-04-26 08:39:31 +02:00

.gitignore

Initialization support for all iCE40 bram modes

2015-04-26 08:39:31 +02:00

arith_map.v

Fixed trailing whitespaces

2015-07-02 11:14:30 +02:00

brams_init.py

Switched to Python 3

2015-08-22 09:59:33 +02:00

brams_map.v

Fixed WE/RE usage in iCE40 BRAM mapping

2015-11-24 10:51:34 +01:00

brams.txt

Added read-enable to memory model

2015-09-25 12:23:11 +02:00

cells_map.v

Improving vpr output support.

2018-04-18 16:55:12 -07:00

cells_sim.v

Avoid mixing module port declaration styles in ice40 cells_sim.v

2018-05-17 13:54:43 +02:00

ice40_ffinit.cc

Minor fixes in ice40_ff* passes for sloppy SB_DFF instantiations

2016-07-08 14:41:36 +02:00

ice40_ffssr.cc

Minor fixes in ice40_ff* passes for sloppy SB_DFF instantiations

2016-07-08 14:41:36 +02:00

ice40_opt.cc

Fix ice40_opt for cases where a port is connected to a signal with width != 1

2018-06-11 18:12:42 +02:00

latches_map.v

Added synth_ice40 support for latches via logic loops

2016-05-06 23:02:37 +02:00

Makefile.inc

Added synth_ice40 support for latches via logic loops

2016-05-06 23:02:37 +02:00

synth_ice40.cc

Add "synth_ice40 -json"

2018-06-13 13:35:10 +02:00