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yosys/techlibs/gowin
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Pepijn de Vos ab8c521030 fix fsm test with proper clock enable polarity 2019-11-11 17:51:26 +01:00
..
Makefile.inc support bram initialisation 2019-09-05 17:25:51 +02:00
arith_map.v use ADDSUB ALU mode to remove inverters 2019-10-21 12:00:27 +02:00
bram.txt add 32-bit BRAM and byte-enables 2019-10-28 10:33:27 +01:00
brams_init.py support bram initialisation 2019-09-05 17:25:51 +02:00
brams_init3.vh GoWin enablement: DRAM, initial BRAM, DRAM init, DRAM sim and synth_gowin flow 2019-04-12 23:40:02 -05:00
brams_map.v add 32-bit BRAM and byte-enables 2019-10-28 10:33:27 +01:00
cells_map.v fix fsm test with proper clock enable polarity 2019-11-11 17:51:26 +01:00
cells_sim.v add IOBUF 2019-10-28 15:33:05 +01:00
determine_init.cc Fix formatting for msys2 mingw build using GetSize 2019-08-01 17:27:34 +02:00
dram.txt GoWin enablement: DRAM, initial BRAM, DRAM init, DRAM sim and synth_gowin flow 2019-04-12 23:40:02 -05:00
drams_map.v GoWin enablement: DRAM, initial BRAM, DRAM init, DRAM sim and synth_gowin flow 2019-04-12 23:40:02 -05:00
synth_gowin.cc add IOBUF 2019-10-28 15:33:05 +01:00