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luke
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yosys
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3216f9420e2f5aed0aa3e38ff89ab616db9b0849
yosys
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techlibs
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Clifford Wolf
ec05242c27
Smaller default parameters in $mem simlib model
2015-02-15 00:20:05 +01:00
..
cmos
Added test comments to techlibs/cmos/cmos_cells.lib
2014-01-29 10:51:02 +01:00
common
Smaller default parameters in $mem simlib model
2015-02-15 00:20:05 +01:00
xilinx
Disabled (unused) Xilinx tristate buffers
2015-02-04 16:33:59 +01:00
.gitignore
added .gitignore files
2013-01-05 11:19:11 +01:00