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mirror of https://github.com/YosysHQ/yosys.git synced 2026-08-29 01:24:25 +02:00
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32082477b50aaeb89101249daa52d9de48d3237b
yosys/techlibs/ecp5
T
History
Lofty 32082477b5 ice40, ecp5: enable ABC9 by default
2023-11-03 08:52:54 +00:00
..
tests
ecp5: Add simulation equivalence check for Diamond FF implementations
2019-08-30 13:27:36 +01:00
arith_map.v
Use HTTPS for website links, gatecat email
2021-06-09 12:16:56 +02:00
brams_map.v
ecp5: Use memory_libmap pass.
2022-05-18 17:32:56 +02:00
brams.txt
ecp5: Use memory_libmap pass.
2022-05-18 17:32:56 +02:00
cells_bb.v
Add additional iopad_external_pin attributes
2023-03-20 09:17:22 +01:00
cells_ff.vh
Fix bitwidth mismatch; suppresses iverilog warning
2019-12-11 13:02:07 -08:00
cells_io.vh
Add iopad_external_pin to some basic io primitives
2023-03-20 09:17:22 +01:00
cells_map.v
ecp5: Add support for mapping aldff.
2021-10-27 16:18:05 +02:00
cells_sim.v
ecp5: Remove TRELLIS_SLICE and add TRELLIS_COMB model
2023-04-06 10:18:48 +01:00
dsp_map.v
ecp5: Force SIGNED ports to be 1 bit
2020-04-16 16:38:19 +01:00
latches_map.v
ecp5: Add latch inference
2018-10-19 15:16:40 +01:00
lutrams_map.v
ecp5: Use memory_libmap pass.
2022-05-18 17:32:56 +02:00
lutrams.txt
ecp5: Use memory_libmap pass.
2022-05-18 17:32:56 +02:00
Makefile.inc
ecp5_gsr -> lattice_gsr, change opt_lut_ins to accept lattice as tech
2023-08-22 10:50:11 +02:00
synth_ecp5.cc
ice40, ecp5: enable ABC9 by default
2023-11-03 08:52:54 +00:00
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