mirror of https://github.com/YosysHQ/yosys.git
69 lines
1.9 KiB
Tcl
69 lines
1.9 KiB
Tcl
yosys -import
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set tmp_v "opt_boundary_random_tmp.v"
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proc emit_case {case_id width op0 op1 op2} {
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global tmp_v
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set fh [open $tmp_v w]
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puts $fh "module m(input \[$width-1:0\] a, input \[$width-1:0\] b, input \[$width-1:0\] c, input \[$width-1:0\] d, output \[$width-1:0\] y);"
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puts $fh " wire \[$width-1:0\] t0 = a $op0 b;"
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puts $fh " wire \[$width-1:0\] t1 = t0 $op1 c;"
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puts $fh " assign y = t1 $op2 d;"
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puts $fh "endmodule"
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puts $fh ""
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set top_width [expr {$width * 4}]
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puts $fh "module top(input \[$top_width-1:0\] a, input \[$top_width-1:0\] b, input \[$top_width-1:0\] c, input \[$top_width-1:0\] d, output \[$top_width-1:0\] y);"
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puts $fh " genvar i;"
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puts $fh " generate"
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puts $fh " for (i = 0; i < 4; i = i + 1) begin : gen"
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puts $fh " m u("
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puts $fh " .a({a\[i*$width +: $width-1\], a\[i*$width + $width-1\]}),"
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puts $fh " .b(b\[i*$width +: $width\]),"
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puts $fh " .c(c\[i*$width +: $width\]),"
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puts $fh " .d(d\[i*$width +: $width\]),"
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puts $fh " .y(y\[i*$width +: $width\])"
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puts $fh " );"
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puts $fh " end"
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puts $fh " endgenerate"
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puts $fh "endmodule"
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close $fh
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log -header "randomized boundary case $case_id"
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log -push
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design -reset
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read_verilog $tmp_v
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hierarchy -top top
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yosys proc
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opt_expr
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opt_clean
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design -save start
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flatten
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design -save gold
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design -load start
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opt_boundary -max_cells 4
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opt_clean
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flatten
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design -save gate
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design -reset
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design -copy-from gold -as gold A:top
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design -copy-from gate -as gate A:top
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yosys rename -hide
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equiv_make gold gate equiv
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equiv_simple equiv
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equiv_status -assert equiv
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log -pop
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}
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set ops [list "&" "|" "^"]
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for {set i 0} {$i < 12} {incr i} {
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set width [expr {2 + ($i % 5)}]
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set op0 [lindex $ops [expr {$i % 3}]]
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set op1 [lindex $ops [expr {($i / 3) % 3}]]
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set op2 [lindex $ops [expr {($i / 9) % 3}]]
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emit_case $i $width $op0 $op1 $op2
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}
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file delete -force $tmp_v
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