yosys/passes
Eddie Hung 304e5f9ea4 Merge remote-tracking branch 'origin/master' into xaig_dff 2019-10-08 13:03:06 -07:00
..
cmds Add "check -allow-tbuf" 2019-10-03 11:49:56 +02:00
equiv Add -async2sync to help text as per @daveshah1 2019-10-04 10:17:46 -07:00
fsm RTLIL::S{0,1} -> State::S{0,1} 2019-08-07 11:12:38 -07:00
hierarchy Adopt @cliffordwolf's suggestion 2019-09-03 12:18:50 -07:00
memory stoi -> atoi 2019-08-07 11:09:17 -07:00
opt Fix handling of z_digit "?" and fix optimization of cmp with "z" 2019-09-13 13:39:39 +02:00
pmgen Merge pull request #1432 from YosysHQ/eddie/fix1427 2019-10-08 12:38:29 -07:00
proc proc_clean: fix order of switch insertion. 2019-08-19 16:44:23 +00:00
sat Revert "Be mindful that sigmap(wire) could have dupes when checking \init" 2019-10-08 12:41:24 -07:00
techmap Use "abc9_period" attribute for delay target 2019-10-07 15:03:44 -07:00
tests Document (* gentb_skip *) attr for test_autotb 2019-09-18 12:41:35 -07:00