mirror of https://github.com/YosysHQ/yosys.git
26dc01102e
According to the latest documentation from GOWIN - "UG285-1.4E Gowin BSRAM & SSRAM User Guide" The dual port BSRAM of all 55nm devices (including GW1N, GW2A and GW1A series) does not support the read-before-write mode (WRITE_MODE = 2) Signed-off-by: YRabbit <rabbit@yrabbit.cyou> |
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| .. | ||
| Makefile.inc | ||
| adc.v | ||
| arith_map.v | ||
| brams.txt | ||
| brams_map.v | ||
| brams_map_gw5a.v | ||
| cells_map.v | ||
| cells_sim.v | ||
| cells_xtra.py | ||
| cells_xtra_gw1n.v | ||
| cells_xtra_gw2a.v | ||
| cells_xtra_gw5a.v | ||
| dsp_map.v | ||
| lutrams.txt | ||
| lutrams_map.v | ||
| synth_gowin.cc | ||