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mirror of https://github.com/YosysHQ/yosys.git synced 2026-09-03 11:18:31 +02:00
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2e78daf1ca68068ca9fa02eca1cc10e64d92cb11
yosys/frontends
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Eddie Hung a0afa1787e aiger: fixes for ports that have start_offset != 0
2020-05-02 10:00:32 -07:00
..
aiger
aiger: fixes for ports that have start_offset != 0
2020-05-02 10:00:32 -07:00
ast
Clear current_scope when done with RTLIL generation, fixes #1837
2020-04-22 14:51:20 +02:00
blif
kernel: big fat patch to use more ID::*, otherwise ID(*)
2020-04-02 09:51:32 -07:00
ilang
ilang, ast: Store parameter order and default value information.
2020-04-21 19:09:00 +02:00
json
…
liberty
kernel: big fat patch to use more ID::*, otherwise ID(*)
2020-04-02 09:51:32 -07:00
rpc
Add WASI platform support.
2020-04-30 18:56:25 +00:00
verific
verific: ignore anonymous enums
2020-04-30 07:48:47 -07:00
verilog
Set Verilog source location for explicit blocks (begin ... end).
2020-04-17 06:23:03 +00:00
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