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yosys/tests
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Zachary Snow 2e697f5655 verilog: check for module scope identifiers during width detection 
The recent fix for case expression width detection causes the width of
the expressions to be queried before they are simplified. Because the
logic supporting module scope identifiers only existed in simplify,
looking them up would fail during width detection. This moves the logic
to a common helper used in both simplify() and detectSignWidthWorker().
 		2021-06-08 15:03:16 -04:00
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aiger switch argument order to work with macOS getopt 2020-09-23 12:48:26 +02:00
arch memory_bram: Reuse extract_rdff helper for make_outreg. 2021-05-25 22:42:03 +02:00
asicworld Fix FIRRTL to Verilog process instance subfield assignment. 2019-02-25 16:18:13 -08:00
blif tests/blif: Add missing gitignore 2021-05-20 12:49:51 +02:00
bram tests/bram: Do not generate write address collisions. 2021-03-08 16:53:03 +01:00
errors
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fsm tests: fsm to use a randomly-generated seed 2020-04-24 14:31:33 -07:00
hana
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liberty dfflibmap: Refactor to use dfflegalize internally. 2020-07-09 18:51:03 +02:00
lut Forgot to commit 2019-07-16 12:44:26 -07:00
memfile Added 'set -e' into tests/memfile/run-test.sh 2020-02-06 10:45:40 -03:00
memories tests: Parallelize 2020-09-21 15:07:02 +02:00
opt memory_map: Improve start_offset handling. 2021-05-31 17:45:21 +02:00
opt_share tests: Parallelize 2020-09-21 15:07:02 +02:00
proc proc_arst: Add special-casing of clock signal in conditionals. 2021-03-15 17:17:29 +01:00
realmath
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rpc rpc test: make frontend listen before launching yosys & introduce safeguard if yosys errors 2020-03-06 15:29:01 +01:00
sat assertpmux: Fix crash on unused $pmux output. 2021-02-22 23:30:28 +01:00
select Merge pull request #1949 from YosysHQ/eddie/select_blackbox 2020-04-22 15:35:05 -07:00
share
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simple verilog: check for module scope identifiers during width detection 2021-06-08 15:03:16 -04:00
simple_abc9 abc9: fix SCC issues (#2694) 2021-03-29 22:01:57 -07:00
smv
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sva Fix "verific -extnets" for more complex situations 2019-03-26 14:17:46 +01:00
svinterfaces Fix typo in tests/svinterfaces/runone.sh 2019-05-03 14:40:51 +02:00
svtypes verilog: check entire user type stack for type definition 2021-03-21 19:35:13 -04:00
techmap Add tests for some common techmap files. 2021-02-24 01:07:34 +01:00
tools memory_dff: Remove now-useless write port handling. 2021-03-08 20:16:29 +01:00
unit
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various abc9: uniquify blackboxes like whiteboxes (#2695) 2021-03-29 22:02:06 -07:00
verilog mem2reg: tolerate out of bounds constant accesses 2021-06-08 15:02:57 -04:00
vloghtb
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gen-tests-makefile.sh tests: Parallelize 2020-09-21 15:07:02 +02:00