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51 lines
1.9 KiB
Verilog
51 lines
1.9 KiB
Verilog
// Test cases for proc_mux dominant-value optimization.
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//
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// When a full_case switch has a majority of arms assigning the same value to a
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// signal bit, proc_mux uses that dominant value as the starting point instead
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// of Sx. Arms that produce the dominant value are then skipped (the mux
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// condition evaluates to "when == else"), avoiding spurious $eq/$mux cells.
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// dominant_explicit: 3 of 4 arms assign the same constants (dominant values).
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// Expected after proc: one $mux per output word, one $logic_not for the
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// selector — zero $eq cells, zero $pmux cells.
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module dominant_explicit(input [1:0] s, output reg [2:0] y, output reg [1:0] z);
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always @* begin
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y = 3'b001;
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z = 2'b00;
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case (s)
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2'b00: begin y = 3'b110; z = 2'b11; end // only arm that differs
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2'b01: begin y = 3'b001; z = 2'b00; end // explicit dominant
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2'b10: begin y = 3'b001; z = 2'b00; end // explicit dominant
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2'b11: begin y = 3'b001; z = 2'b00; end // explicit dominant
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endcase
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end
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endmodule
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// dominant_wire: dominant value is an input wire (not a constant).
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// Expected after proc: 1 $logic_not + 1 $mux, no $eq/$pmux.
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module dominant_wire(input [1:0] s, input [2:0] a, output reg [2:0] y);
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always @* begin
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y = a;
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case (s)
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2'b00: y = 3'b110; // only arm that differs
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2'b01: y = a; // explicit dominant
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2'b10: y = a; // explicit dominant
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2'b11: y = a; // explicit dominant
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endcase
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end
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endmodule
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// no_dominant: all four arms assign distinct values — no majority.
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// The optimization must NOT fire; behavior must be unchanged.
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// Expected after proc: $eq cells for each non-zero compare arm, $pmux.
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module no_dominant(input [1:0] s, input [2:0] a, b, c, d, output reg [2:0] y);
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always @* begin
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case (s)
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2'b00: y = a;
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2'b01: y = b;
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2'b10: y = c;
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2'b11: y = d;
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endcase
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end
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endmodule
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