Logo
Explore Help
Sign In
luke/yosys
Watch 1
Star 0
Fork 0
mirror of https://github.com/YosysHQ/yosys.git synced 2026-09-04 11:29:42 +02:00
Code Issues Packages Projects Releases Wiki Activity
Files
2cf0b5c1575b2ea4f8d949854eab7ab2bfdcd10e
yosys/passes
T
History
Robert Ou 9a64ba3338 abc: Allow +/ filenames in the abc command
2017-08-14 12:11:11 -07:00
..
cmds
Add $alu to list of supported cells for "stat -width"
2017-07-14 11:32:49 +02:00
equiv
Fix equiv_simple, old behavior now available with "equiv_simple -short"
2017-04-28 18:57:53 +02:00
fsm
Squelch trailing whitespace
2017-04-12 15:11:09 +02:00
hierarchy
Add error for cell output ports that are connected to constants
2017-07-22 15:08:30 +02:00
memory
Typo fix.
2016-09-08 10:57:16 +03:00
opt
Add support for set-reset cell variants to opt_rmdff
2017-08-09 13:29:52 +02:00
proc
Added $global_clock verilog syntax support for creating $ff cells
2016-10-14 12:33:56 +02:00
sat
Add "setundef -anyseq"
2017-05-28 11:59:05 +02:00
techmap
abc: Allow +/ filenames in the abc command
2017-08-14 12:11:11 -07:00
tests
Add $live and $fair cell types, add support for s_eventually keyword
2017-02-25 10:36:39 +01:00
Powered by Gitea Version: 1.27.2 Page: 181ms Template: 3ms
Auto
English
Bahasa Indonesia Deutsch English Español Français Gaeilge Italiano Latviešu Magyar nyelv Nederlands Polski Português de Portugal Português do Brasil Suomi Svenska Türkçe Čeština Ελληνικά Български Русский Українська فارسی മലയാളം 日本語 简体中文 繁體中文(台灣) 繁體中文(香港) 한국어
Licenses API