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mirror of https://github.com/YosysHQ/yosys.git synced 2026-10-06 10:03:36 +02:00
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2c96ecc5f7d88cfd8dbddc3e5f45fb0a2a9bb6d3
yosys/passes
T
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Miodrag Milanovic 2c96ecc5f7 setInitState can be only one altering values
2022-04-02 19:13:15 +02:00
..
cmds
Merge pull request #2019 from boqwxp/glift
2022-02-11 15:51:24 +01:00
equiv
Fixing old e-mail addresses and deadnames
2021-06-08 00:39:36 +02:00
fsm
Fixing old e-mail addresses and deadnames
2021-06-08 00:39:36 +02:00
hierarchy
verilog: use derived module info to elaborate cell connections
2021-10-25 18:25:50 -07:00
memory
memory_bram: Make use of new mem emulation functions to map more RAMs.
2022-01-27 19:31:27 +01:00
opt
opt_merge: Add -keepdc option required for formal verification
2022-04-01 21:03:20 +02:00
pmgen
Update comment
2022-02-02 03:21:09 +01:00
proc
proc_dff: Emit $aldff.
2021-10-27 14:14:24 +02:00
sat
setInitState can be only one altering values
2022-04-02 19:13:15 +02:00
techmap
Merge pull request #3194 from Ravenslofty/abc9-flow3mfs
2022-03-28 15:51:04 +01:00
tests
Add $bmux and $demux cells.
2022-01-28 23:34:41 +01:00
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