yosys/backends at 2c95dfcb5bbce7f5b19d36d8d5d1258f48aaedcf - yosys - Gitea: Git with a cup of tea

luke/yosys

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Clifford Wolf c9672e2e2e Fix handling of zero-length cell connections in SMT2 back-end

Signed-off-by: Clifford Wolf <[email protected]>

2018-02-08 19:12:12 +01:00

..

Fix generation of multiple outputs for same AIG node in write_aiger

2017-07-05 14:23:54 +02:00

Add $_ANDNOT_ and $_ORNOT_ gates

2017-05-17 09:08:29 +02:00

Add "no driver for signal bit" error msg to btor back-end

2017-12-24 17:30:36 +01:00

Fix the fixed handling of x-bits in EDIF back-end

2017-07-11 17:45:29 +02:00

More progress on Firrtl backend.

2017-02-13 11:17:53 -08:00

Fixed gcc 7.2 "statement will never be executed" warning

2018-02-03 14:31:47 +01:00

Added "yosys -D" feature

2016-04-21 23:28:37 +02:00

Add attributes and parameter support to JSON front-end

2017-07-10 13:17:38 +02:00

Add workaround for CBMC bug to SimpleC back-end

2017-05-17 21:07:54 +02:00

Fix handling of zero-length cell connections in SMT2 back-end

2018-02-08 19:12:12 +01:00

Add $_ANDNOT_ and $_ORNOT_ gates

2017-05-17 09:08:29 +02:00

Also escape "=" in spice output

2016-05-20 16:43:13 +02:00

Add write_table command

2017-07-05 12:13:53 +02:00

Add $shiftx support to verilog front-end

2017-10-07 13:40:54 +02:00