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yosys
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2bcd55f1aec8ff2108db835f96e8abd4e89e4be6
yosys
/
tests
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arch
T
History
Eddie Hung
6e866030c2
Combine tests to check multiple clock domains
2020-01-02 14:38:59 -08:00
..
anlogic
Call equiv_opt with -multiclock and -assert
2019-12-31 18:39:32 -08:00
common
Merge pull request
#1574
from YosysHQ/eddie/xilinx_lutram
2019-12-16 21:48:21 -08:00
ecp5
Do not do call equiv_opt when no sim model exists
2019-12-31 18:40:30 -08:00
efinix
Call equiv_opt with -multiclock and -assert
2019-12-31 18:39:32 -08:00
gowin
Call equiv_opt with -multiclock and -assert
2019-12-31 18:39:32 -08:00
ice40
Revert insertion of 'reg', leave note behind
2020-01-01 09:05:46 -08:00
xilinx
Combine tests to check multiple clock domains
2020-01-02 14:38:59 -08:00
run-test.sh
Add simcells.v, simlib.v, and some output
2019-06-27 11:13:49 -07:00
