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mirror of https://github.com/YosysHQ/yosys.git synced 2026-08-30 09:58:22 +02:00
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2bcd55f1aec8ff2108db835f96e8abd4e89e4be6
yosys/techlibs/gowin
T
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whitequark f8d5920a7e Merge pull request #1604 from whitequark/unify-ram-naming
Harmonize BRAM/LUTRAM descriptions across all of Yosys
2020-01-02 21:06:17 +00:00
..
.gitignore
gowin: Add missing .gitignore entries
2019-11-22 14:40:36 +01:00
arith_map.v
use ADDSUB ALU mode to remove inverters
2019-10-21 12:00:27 +02:00
brams_init3.vh
GoWin enablement: DRAM, initial BRAM, DRAM init, DRAM sim and synth_gowin flow
2019-04-12 23:40:02 -05:00
brams_init.py
support bram initialisation
2019-09-05 17:25:51 +02:00
brams_map.v
add 32-bit BRAM and byte-enables
2019-10-28 10:33:27 +01:00
brams.txt
Harmonize BRAM/LUTRAM descriptions across all of Yosys.
2020-01-01 12:30:00 +00:00
cells_map.v
attempt to fix formatting
2019-11-25 14:50:34 +01:00
cells_sim.v
add IOBUF
2019-10-28 15:33:05 +01:00
determine_init.cc
Fix formatting for msys2 mingw build using GetSize
2019-08-01 17:27:34 +02:00
lutrams_map.v
Harmonize BRAM/LUTRAM descriptions across all of Yosys.
2020-01-01 12:30:00 +00:00
lutrams.txt
Harmonize BRAM/LUTRAM descriptions across all of Yosys.
2020-01-01 12:30:00 +00:00
Makefile.inc
Harmonize BRAM/LUTRAM descriptions across all of Yosys.
2020-01-01 12:30:00 +00:00
synth_gowin.cc
Merge pull request #1604 from whitequark/unify-ram-naming
2020-01-02 21:06:17 +00:00
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