mirror of https://github.com/YosysHQ/yosys.git
189 lines
3.1 KiB
Plaintext
189 lines
3.1 KiB
Plaintext
log -header "Infer $icg from latch-based clock gate with scan enable"
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log -push
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design -reset
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read_verilog -sv <<EOF
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module top(input logic CK, EN, SE, output logic Q);
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logic en_ff;
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logic enable;
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assign enable = EN | SE;
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always_latch
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if (!CK)
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en_ff = enable;
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assign Q = CK & en_ff;
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endmodule
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EOF
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hierarchy -auto-top
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proc
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opt
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select -assert-count 1 t:$dlatch
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select -assert-count 1 t:$and t:$logic_and
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select -assert-count 1 t:$or t:$logic_or
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select -assert-count 0 t:$icg
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infer_icg
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clean
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check -assert
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select -assert-count 1 t:$icg
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select -assert-count 0 t:$dlatch
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select -assert-count 0 t:$and t:$logic_and
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select -assert-count 0 t:$or t:$logic_or
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design -reset
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log -pop
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log -header "Infer $icg from latch-based clock gate without scan enable"
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log -push
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design -reset
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read_verilog -sv <<EOF
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module top(input logic CK, EN, output logic Q);
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logic en_ff;
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always_latch
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if (!CK)
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en_ff = EN;
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assign Q = en_ff & CK;
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endmodule
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EOF
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hierarchy -auto-top
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proc
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opt
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infer_icg
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clean
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check -assert
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select -assert-count 1 t:$icg
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select -assert-count 0 t:$dlatch
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select -assert-count 0 t:$and t:$logic_and
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design -reset
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log -pop
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log -header "Infer $icg from active-high latch on inverted clock"
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log -push
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design -reset
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read_verilog -sv <<EOF
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module top(input logic CK, EN, SE, output logic Q);
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logic en_ff;
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logic enable;
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logic nCK;
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assign enable = EN | SE;
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assign nCK = !CK;
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always_latch
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if (nCK)
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en_ff = enable;
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assign Q = CK & en_ff;
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endmodule
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EOF
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hierarchy -auto-top
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proc
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opt
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infer_icg
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clean
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check -assert
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select -assert-count 1 t:$icg
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select -assert-count 0 t:$dlatch
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select -assert-count 0 t:$and t:$logic_and
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select -assert-count 0 t:$or t:$logic_or
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design -reset
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log -pop
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log -header "Infer $icg from active-high latch on inverted clock without scan enable"
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log -push
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design -reset
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read_verilog -sv <<EOF
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module top(input logic CK, EN, output logic Q);
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logic en_ff;
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logic nCK;
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assign nCK = !CK;
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always_latch
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if (nCK)
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en_ff = EN;
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assign Q = CK & en_ff;
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endmodule
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EOF
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hierarchy -auto-top
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proc
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opt
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infer_icg
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clean
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check -assert
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select -assert-count 1 t:$icg
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select -assert-count 0 t:$dlatch
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select -assert-count 0 t:$and t:$logic_and
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design -reset
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log -pop
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log -header "Infer $icg from high-idle OR clock gate"
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log -push
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design -reset
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read_verilog -sv <<EOF
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module top(input logic CK, EN, SE, output logic Q);
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logic en_ff;
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logic enable;
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assign enable = EN | SE;
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always_latch
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if (CK)
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en_ff = enable;
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assign Q = CK | !en_ff;
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endmodule
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EOF
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hierarchy -auto-top
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proc
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opt
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infer_icg
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clean
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check -assert
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select -assert-count 1 t:$icg
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select -assert-count 0 t:$dlatch
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select -assert-count 0 t:$or t:$logic_or
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design -reset
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log -pop
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log -header "Infer $icg from high-idle OR clock gate without scan enable"
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log -push
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design -reset
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read_verilog -sv <<EOF
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module top(input logic CK, EN, output logic Q);
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logic en_ff;
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always_latch
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if (CK)
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en_ff = EN;
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assign Q = CK | !en_ff;
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endmodule
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EOF
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hierarchy -auto-top
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proc
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opt
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infer_icg
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clean
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check -assert
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select -assert-count 1 t:$icg
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select -assert-count 0 t:$dlatch
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select -assert-count 0 t:$or t:$logic_or
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design -reset
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log -pop
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