mirror of https://github.com/YosysHQ/yosys.git
14 lines
445 B
Plaintext
14 lines
445 B
Plaintext
read_verilog ../common/add_sub.v
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hierarchy -top top
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proc
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design -save orig
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equiv_opt -assert -map +/analogdevices/cells_sim.v synth_analogdevices -noiopad # equivalency check
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design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design)
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cd top # Constrain all select calls below inside the top module
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stat
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select -assert-count 8 t:LUT2
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select -assert-count 2 t:CRY4
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select -assert-none t:LUT2 t:CRY4 %% t:* %D
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