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mirror of https://github.com/YosysHQ/yosys.git synced 2026-09-07 20:36:44 +02:00
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2aff7b2a47d2ad65ff34e10f008733da9ef50c4a
yosys/passes
T
History
Clifford Wolf 4e43cb7317 Added _TECHMAP_REPLACE_ feature to techmap
2014-02-20 23:42:07 +01:00
..
abc
Added abc -keepff option
2014-02-14 11:28:42 +01:00
cmds
Added "design -push" and "design -pop"
2014-02-20 23:28:59 +01:00
fsm
Fixes in fsm detect/extract for better detection of non-fsm circuits
2013-12-06 12:53:20 +01:00
hierarchy
Implemented read_verilog -defer
2014-02-13 13:59:13 +01:00
memory
Fixed bug in collecting of RD_TRANSPARENT parameter in memory_collect
2014-02-08 19:13:19 +01:00
opt
Fixed handling of "keep" attribute on wires in opt_clean
2014-02-16 21:58:27 +01:00
proc
Tiny cleanup in proc_mux.cc
2014-01-03 16:54:59 +01:00
sat
Added "sat -dump_cnf"
2014-02-18 09:29:08 +01:00
techmap
Added _TECHMAP_REPLACE_ feature to techmap
2014-02-20 23:42:07 +01:00
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