mirror of https://github.com/YosysHQ/yosys.git
23 lines
568 B
Plaintext
23 lines
568 B
Plaintext
read_verilog rams_init_file.v
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hierarchy -top rams_init_file
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proc
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memory -nomap
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equiv_opt -run :prove -map +/xilinx/cells_sim.v synth_xilinx
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memory
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opt -full
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# TODO
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#equiv_opt -run prove: -assert null
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miter -equiv -flatten -make_assert -make_outputs gold gate miter
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#sat -verify -prove-asserts -tempinduct -show-inputs -show-outputs miter
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design -load postopt
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cd rams_init_file
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stat
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#Vivado synthesizes 1 RAMB18E1.
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select -assert-count 1 t:BUFG
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select -assert-count 32 t:FDRE
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select -assert-count 32 t:RAM64X1D
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select -assert-none t:BUFG t:FDRE t:RAM64X1D %% t:* %D
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