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mirror of https://github.com/YosysHQ/yosys.git synced 2026-08-29 01:24:25 +02:00
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29db96fa1ff89a8224f8ae3c51c754e16a34c31c
yosys/techlibs
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Eddie Hung 29db96fa1f Revert "Vivado does not like zero width port connections"
This reverts commit 895e2befa7.
2019-09-23 19:52:54 -07:00
..
achronix
…
anlogic
make note that it is for latch mode
2019-09-18 17:48:16 +02:00
common
Fix signedness bug
2019-09-20 10:11:36 -07:00
coolrunner2
Fix spacing
2019-08-06 16:47:55 -07:00
easic
…
ecp5
Merge remote-tracking branch 'origin/master' into xc7dsp
2019-09-05 13:01:27 -07:00
efinix
better handling of lut and begin/end add
2019-09-18 17:45:07 +02:00
gowin
Fix formatting for msys2 mingw build using GetSize
2019-08-01 17:27:34 +02:00
greenpak4
…
ice40
Re-add DSP_A_MINWIDTH, remove unnec. opt_expr -fine from synth_ice40
2019-09-20 09:02:29 -07:00
intel
techlibs/intel: Clean up Makefile
2019-08-05 11:22:11 -07:00
sf2
…
xilinx
Revert "Vivado does not like zero width port connections"
2019-09-23 19:52:54 -07:00
.gitignore
…
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