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mirror of https://github.com/YosysHQ/yosys.git synced 2026-09-06 20:12:09 +02:00
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29c8a3bef95bf2865fa2c5c52a9b20046730939c
yosys/passes
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N. Engelhardt e4f11eb0a0 Merge pull request #4228 from povik/synth-inject
synth: Introduce `-extra-map` for amending techmap
2024-03-11 14:55:45 +01:00
..
cmds
rename -witness: Bug fix and rename formal cells
2024-03-04 16:53:03 +01:00
equiv
equiv_simple: Take FFs into account for driver map
2024-02-21 12:05:52 +01:00
fsm
add option to fsm_detect to ignore self-resetting
2023-01-30 16:12:53 +01:00
hierarchy
hierarchy: Without a known top module, derive all deferred modules
2024-02-06 10:31:40 +01:00
memory
opt_mem, memory_*: Refuse to operate in presence of processes
2024-02-23 12:27:53 +01:00
opt
opt_mem, memory_*: Refuse to operate in presence of processes
2024-02-23 12:27:53 +01:00
pmgen
Address SigBit/SigSpec confusion issues under c++20
2024-02-08 17:48:36 +01:00
proc
Merge pull request #4218 from kivikakk/proc_rom-actionless-switch
2024-02-19 16:21:40 +01:00
sat
Merge pull request #3972 from nakengelhardt/celledges_shift_ops
2024-03-08 09:35:47 +01:00
techmap
Merge pull request #4228 from povik/synth-inject
2024-03-11 14:55:45 +01:00
tests
Add $bmux and $demux cells.
2022-01-28 23:34:41 +01:00
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