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mirror of https://github.com/YosysHQ/yosys.git synced 2026-09-01 10:39:10 +02:00
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28e99f2b8c50557e0376fbded1c77236a987ecec
yosys/techlibs
T
History
Miodrag Milanovic 72bec94ef4 Add missing file for XO3D
2023-09-01 10:15:51 +02:00
..
achronix
Test fixes for latest iverilog
2022-09-21 15:46:43 +02:00
anlogic
…
common
ast: add PRIORITY to $print cells
2023-08-11 04:46:52 +02:00
coolrunner2
…
easic
…
ecp5
ecp5_gsr -> lattice_gsr, change opt_lut_ins to accept lattice as tech
2023-08-22 10:50:11 +02:00
efinix
…
fabulous
fabulous: Add support for LUT6s
2023-04-12 18:42:09 +02:00
gatemate
gatemate: Prevent implicit declaration of ram_{we,en}
2023-06-05 19:08:44 +02:00
gowin
Merge pull request #3737 from yrabbit/all-primitives-script
2023-05-09 11:13:51 +02:00
greenpak4
…
ice40
ice40: Fix path delay definitions
2023-03-10 10:48:05 +01:00
intel
Fitting help messages to 80 character width
2022-08-24 10:40:57 +12:00
intel_alm
intel_alm: re-enable 8x40-bit M10K support
2023-05-29 06:42:03 +01:00
lattice
Add missing file for XO3D
2023-09-01 10:15:51 +02:00
nexus
nexus: Fix BRAM write enable in PDP mode
2023-01-04 17:59:36 +01:00
quicklogic
Fitting help messages to 80 character width
2022-08-24 10:40:57 +12:00
sf2
Test fixes for latest iverilog
2022-09-21 15:46:43 +02:00
xilinx
Update Xilinx cell definitions, fixes #3699
2023-03-23 09:44:36 +01:00
.gitignore
…
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