mirror of https://github.com/YosysHQ/yosys.git
143 lines
6.8 KiB
Python
143 lines
6.8 KiB
Python
#####################################################################
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# A script to generate cell sim for pcounters
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#####################################################################
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import os
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from os.path import dirname, abspath
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import argparse
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import logging
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import csv
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import pcounter_ip_template_generator
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#####################################################################
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# Error codes
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#####################################################################
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error_codes = {"SUCCESS": 0, "ERROR": 1, "FILE_ERROR": 3}
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#####################################################################
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# Initialize logger
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#####################################################################
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logging.basicConfig(format="%(levelname)s: %(message)s", level=logging.ERROR)
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def generate_file_header(f0):
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f0.write("//-------------------------------------------------\n")
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f0.write("// IMPORTANT: This file is auto generated!!! DO NOT MODIFY BY HAND!!!\n")
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f0.write("//-------------------------------------------------\n")
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f0.write("// Pcounter Primitives\n")
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f0.write("// Naming convention:\n")
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f0.write(
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"// pcounter<size>_clk<trigger_type>_<reset_type>rst<reset_poloarity>_<event_function>\n"
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)
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f0.write(
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"// size: [N | <int> ] ranges from 0 to 31, representing the number of bits. N is a parameterized design, which is supposed not be exposed to users\n"
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)
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f0.write("// trigger_type: [p|n] denotes [rising edge (posedge) | falling edge (negedge) ]\n")
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f0.write("// reset_type: [a|s] denotes [ asynchronous | synchronous ]\n")
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f0.write("// reset_polarity: [p|n] denotes [ active-high | active-low ]\n")
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f0.write(
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"// event_function : [ load | add | sub | sr | sl ] denotes [ load | add | substract | shift right | shift left ] on the data_i values\n"
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)
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def generate_pcounter_ips(fpath):
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pcnt_ip_tmpl_gen = pcounter_ip_template_generator.PcounterIpTemplateGenerator()
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cnt = 0
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with open(fpath, "w") as cell_sim_fh:
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generate_file_header(cell_sim_fh)
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for clk_type in pcnt_ip_tmpl_gen.clock_types():
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for rst_type in pcnt_ip_tmpl_gen.reset_types():
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for rst_polar in pcnt_ip_tmpl_gen.reset_polarities():
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for event_type in pcnt_ip_tmpl_gen.event_types():
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logging.info(
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f"Generating IPs: {pcnt_ip_tmpl_gen.ip_template_name(clk_type, rst_type, rst_polar, event_type)} ..."
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)
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logging.debug(
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f"Generating IP template: {pcnt_ip_tmpl_gen.ip_template_name(clk_type, rst_type, rst_polar, event_type)} ..."
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)
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pcnt_ip_tmpl_gen.write_ip_template(
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cell_sim_fh, clk_type, rst_type, rst_polar, event_type
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)
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logging.debug(f"Done")
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cnt += 1
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# Generate full-size (32-bit) version
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d_size = pcnt_ip_tmpl_gen.max_data_size()
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logging.debug(
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f"Generating full-sized counter IP: {pcnt_ip_tmpl_gen.ip_name(clk_type, rst_type, rst_polar, event_type, d_size)} ..."
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)
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pcnt_ip_tmpl_gen.write_ip(
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cell_sim_fh, clk_type, rst_type, rst_polar, event_type, d_size
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)
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logging.debug(f"Done")
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cnt += 1
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# Generate half-size (16-bit) version
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d_size = int(pcnt_ip_tmpl_gen.max_data_size() / 2)
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logging.debug(
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f"Generating half-sized counter IP: {pcnt_ip_tmpl_gen.ip_name(clk_type, rst_type, rst_polar, event_type, d_size)} ..."
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)
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pcnt_ip_tmpl_gen.write_ip(
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cell_sim_fh, clk_type, rst_type, rst_polar, event_type, d_size
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)
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logging.debug(f"Done")
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cnt += 1
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# Generate CCB
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logging.info(
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f"Generating ccb-related IPs: {pcnt_ip_tmpl_gen.ccb_ip_template_name(clk_type, rst_type, rst_polar, event_type)} ..."
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)
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logging.debug(
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f"Generating ccb-related IP template: {pcnt_ip_tmpl_gen.ccb_ip_template_name(clk_type, rst_type, rst_polar, event_type)} ..."
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)
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pcnt_ip_tmpl_gen.write_ccb_ip_template(
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cell_sim_fh, clk_type, rst_type, rst_polar, event_type
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)
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logging.debug(f"Done")
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cnt += 1
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d_size = pcnt_ip_tmpl_gen.max_data_size()
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logging.debug(
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f"Generating ccb-related full-sized IP: {pcnt_ip_tmpl_gen.ccb_ip_name(clk_type, rst_type, rst_polar, event_type, d_size)} ..."
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)
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pcnt_ip_tmpl_gen.write_ccb_ip(
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cell_sim_fh, clk_type, rst_type, rst_polar, event_type, d_size
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)
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logging.debug(f"Done")
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cnt += 1
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# Generate half-size (16-bit) version
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d_size = int(pcnt_ip_tmpl_gen.max_data_size() / 2)
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logging.debug(
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f"Generating ccb-related half-sized IP: {pcnt_ip_tmpl_gen.ccb_ip_name(clk_type, rst_type, rst_polar, event_type, d_size)} ..."
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)
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pcnt_ip_tmpl_gen.write_ccb_ip(
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cell_sim_fh, clk_type, rst_type, rst_polar, event_type, d_size
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)
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logging.debug(f"Done")
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cnt += 1
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logging.info(f"Done")
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logging.info(f"Generated {cnt} IPs")
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return 0
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#####################################################################
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# Main function
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#####################################################################
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if __name__ == "__main__":
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# Execute when the module is not initialized from an import statement
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# Parse the options and apply sanity checks
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parser = argparse.ArgumentParser(description="Generate cell sim Verilog for Pcounter")
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parser.add_argument(
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"--file",
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required=True,
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default="cell_sim_pcnt.v",
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help="Path to the .v file that contains pcounter IPs",
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)
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args = parser.parse_args()
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num_error = generate_pcounter_ips(args.file)
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if num_error == 0:
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logging.info("Generation succeed")
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exit(error_codes["SUCCESS"])
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else:
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logging.error("Generation failed in " + str(num_error) + " errors!")
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exit(error_codes["ERROR"])
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