mirror of https://github.com/YosysHQ/yosys.git
385 lines
18 KiB
Verilog
385 lines
18 KiB
Verilog
module mad12x10x22 (clk_i, rst_ni, a_i, b_i, d_i, out_o, mode_i, rst_acc, accsel, cas_g, overflow);
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input [0:47] a_i;
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input [0:39] b_i;
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input [0:59] d_i;
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input [0:12] mode_i;
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output [0:59] out_o;
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input clk_i;
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input rst_ni;
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input rst_acc;
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input accsel;
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input cas_g;
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output overflow;
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dsp #(
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.N_SIZE (12),
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.M_SIZE (10)
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) u_dsp(
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.a_i (a_i),
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.b_i (b_i),
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.out_o (out_o),
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.clk_i (clk_i),
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.rst_ni (rst_ni),
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.d_i (d_i),
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.mode_i (mode_i),
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.rst_acc (rst_acc),
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.accsel (accsel),
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.cas_g (cas_g),
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.overflow (overflow)
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);
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endmodule
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module mad24x20x44 (clk_i, rst_ni, a_i, b_i, d_i, out_o, mode_i, rst_acc, accsel, cas_g, overflow);
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input [0:95] a_i;
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input [0:79] b_i;
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input [0:103] d_i;
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input [0:12] mode_i;
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output [0:103] out_o;
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input clk_i;
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input rst_ni;
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input rst_acc;
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input accsel;
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input cas_g;
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output overflow;
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dsp #(
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.N_SIZE (24),
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.M_SIZE (20)
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) u_dsp(
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.a_i (a_i),
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.b_i (b_i),
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.out_o (out_o),
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.clk_i (clk_i),
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.rst_ni (rst_ni),
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.d_i (d_i),
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.mode_i (mode_i),
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.rst_acc (rst_acc),
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.accsel (accsel),
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.cas_g (cas_g),
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.overflow (overflow)
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);
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endmodule
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//-----------------------------------------------------
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// Design Name : Parameterized DSP block
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// File Name : dsp.v
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// Function : A N*M-bit DSP block which can operate in fracturable modes:
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// 1. four [N/4]*[M/4]-bit multiplication with accumulation
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// 1.1 (combinational)
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// 1.2 (with input registers triggered by rising edge)
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// 1.3 (with output registers triggered by rising edge)
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// 1.4 (with input and output registers triggered by rising edge)
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// 1.5 (with input registers triggered by falling edge)
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// 1.6 (with output registers triggered by falling edge)
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// 1.7 (with input and output registers triggered by falling edge)
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// 2. two [N/2]*[M/2]-bit multipliers
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// 2.1 (combinational)
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// 2.2 (with input registers triggered by rising edge)
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// 2.3 (with output registers triggered by rising edge)
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// 2.4 (with input and output registers triggered by rising edge)
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// 2.5 (with input registers triggered by falling edge)
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// 2.6 (with output registers triggered by falling edge)
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// 2.7 (with input and output registers triggered by falling edge)
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// 3. Single N*M-bit multipliers
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// 3.1 (combinational)
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// 3.2 (with input registers triggered by rising edge)
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// 3.3 (with output registers triggered by rising edge)
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// 3.4 (with input and output registers triggered by rising edge)
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// 3.5 (with input registers triggered by falling edge)
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// 3.6 (with output registers triggered by falling edge)
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// 3.7 (with input and output registers triggered by falling edge)
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// 4. Two [N/4]*[M/4]-bit multiply-accumulators
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// 4.1 (combinational)
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// 4.2 (with input registers triggered by rising edge)
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// 4.3 (with output registers triggered by rising edge)
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// 4.4 (with input and output registers triggered by rising edge)
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// 4.5 (with input registers triggered by falling edge)
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// 4.6 (with output registers triggered by falling edge)
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// 4.7 (with input and output registers triggered by falling edge)
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// 5. One [N/4]*[M/4]-bit multiplier + One [N/4]*[M/4]-bit MAC
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// 5.1 (combinational)
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// 5.2 (with input registers triggered by rising edge)
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// 5.3 (with output registers triggered by rising edge)
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// 5.4 (with input and output registers triggered by rising edge)
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// 5.5 (with input registers triggered by falling edge)
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// 5.6 (with output registers triggered by falling edge)
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// 5.7 (with input and output registers triggered by falling edge)
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// 6. One [N/4]*[M/4]-bit MAC + One [N/4]*[M/4]-bit multiply
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// 6.1 (combinational)
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// 6.2 (with input registers triggered by rising edge)
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// 6.3 (with output registers triggered by rising edge)
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// 6.4 (with input and output registers triggered by rising edge)
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// 6.5 (with input registers triggered by falling edge)
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// 6.6 (with output registers triggered by falling edge)
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// 6.7 (with input and output registers triggered by falling edge)
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// 7. MSB parts [N/2+M/2] of four multipliers
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// 7.1 (combinational)
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// 7.2 (with input registers triggered by rising edge)
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// 7.3 (with output registers triggered by rising edge)
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// 7.4 (with input and output registers triggered by rising edge)
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// 7.5 (with input registers triggered by falling edge)
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// 7.6 (with output registers triggered by falling edge)
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// 7.7 (with input and output registers triggered by falling edge)
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// 8. One [N/4]*[M/4]-bit multiply + MSB parts [N/2+M/2] of four multipliers
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// 8.1 (combinational)
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// 8.2 (with input registers triggered by rising edge)
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// 8.3 (with output registers triggered by rising edge)
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// 8.4 (with input and output registers triggered by rising edge)
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// 8.5 (with input registers triggered by falling edge)
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// 8.6 (with output registers triggered by falling edge)
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// 8.7 (with input and output registers triggered by falling edge)
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// 9. One [N/4]*[M/4]-bit MAC + MSB parts [N/2+M/2] of four multipliers
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// 9.1 (combinational)
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// 9.2 (with input registers triggered by rising edge)
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// 9.3 (with output registers triggered by rising edge)
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// 9.4 (with input and output registers triggered by rising edge)
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// 9.5 (with input registers triggered by falling edge)
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// 9.6 (with output registers triggered by falling edge)
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// 9.7 (with input and output registers triggered by falling edge)
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// - In all the above modes, clock edges can be either positive or negative triggered
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// Coder : Xifan Tang
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//-----------------------------------------------------
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`default_nettype wire
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module dsp (clk_i, rst_ni, a_i, b_i, d_i, out_o, mode_i, rst_acc, accsel, cas_g, overflow);
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// Parameters that can pass through
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parameter N_SIZE = 12; // Default parameter for N
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parameter M_SIZE = 10; // Default parameter for M
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// Local parameters
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localparam A_WIDTH = 4 * N_SIZE; // Default parameter for a
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localparam B_WIDTH = 4 * M_SIZE; // Default parameter for b
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localparam C_WIDTH = N_SIZE + M_SIZE; // Default parameter for cin
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localparam OUT_WIDTH = A_WIDTH / 2 + B_WIDTH / 2; // Default parameter for data output
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parameter P_SIZE = OUT_WIDTH; // Default parameter for previous d
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// Ensure that all the mode bit constants unique!!!
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localparam MODE_BIT_CLK = 0; // Mode bit that controls polarity of the clock signals
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localparam MODE_BIT_REGI_UPPER = 1; // Mode bit that controls the registering of upper part of the inputs
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localparam MODE_BIT_REGI_LOWER = 2; // Mode bit that controls the registering of lower part of the inputs
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localparam MODE_BIT_REGO_UPPER = 3; // Mode bit that controls the registering of upper part of the outputs
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localparam MODE_BIT_REGO_LOWER = 4; // Mode bit that controls the registering of lower part of the outputs
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localparam MODE_BIT_MAC_LSB = 5; // LSB of the mode bits that control the core computing units
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localparam MODE_BIT_MAC_MSB = 8; // MSB of the mode bits that contorl the core computing units
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localparam MODE_BIT_RST = 9; // MSB of the mode bits that contorl the polarity of reset signals
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localparam MODE_BIT_SIGN = 10; //Mode bit that controls valid of the sign bit
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// localparam MODE_BIT_CARRY = 11; //Mode bit that controls valid of the carry bit
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localparam MODE_MUL_INPUT_REG = 11; // Mode bit that controls the registering of the inputs of the multipliers
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localparam MODE_MUL_OUTPUT_REG = 12; // Mode bit that controls the registering of the outputs of the multipliers
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localparam ADDER_REDUNDENT = 8; // Default parameter for adder redundancy
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localparam ADD_ACC_WIDTH = OUT_WIDTH/2 + ADDER_REDUNDENT; // Default accumulating parameter for adder width
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localparam ACC_OUT_WIDTH = OUT_WIDTH + 2*ADDER_REDUNDENT;
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// Ports
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input clk_i;
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input rst_ni;
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input [0:A_WIDTH-1] a_i;
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input [0:B_WIDTH-1] b_i;
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input [0:ACC_OUT_WIDTH-1] d_i;
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output [0:ACC_OUT_WIDTH-1] out_o;
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input [0:12] mode_i;
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output overflow;
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// input cin;
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// output cout;
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input rst_acc; //For accumulate resettable
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input accsel; // Accumulate or add new data
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input cas_g; // Global cascade mode for top level dsp
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wire clk_core;
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wire clr;
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assign clk_core = mode_i[MODE_BIT_CLK] ? clk_i : ~clk_i;
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assign clr = mode_i[MODE_BIT_RST] ? ~rst_ni : rst_ni;
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// Control logic for registering inputs and outputs
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wire [0:A_WIDTH-1] in_a;
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wire [0:B_WIDTH-1] in_b;
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wire [0:ACC_OUT_WIDTH-1] in_d;
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wire [0:ACC_OUT_WIDTH-1] cas_out;
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reg [0:A_WIDTH-1] a_i_reg;
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reg [0:B_WIDTH-1] b_i_reg;
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reg [0:ACC_OUT_WIDTH-1] d_i_reg;
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reg [0:ACC_OUT_WIDTH-1] out_o_reg;
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always @(posedge clk_core or negedge clr) begin
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if (clr == 1'b0) begin
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a_i_reg <= 0;
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b_i_reg <= 0;
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d_i_reg <= 0;
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out_o_reg <= 0;
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end else begin
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a_i_reg <= a_i;
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b_i_reg <= b_i;
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d_i_reg <= d_i;
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out_o_reg <= cas_out;
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end
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end
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assign in_a[0:A_WIDTH/2-1] = mode_i[MODE_BIT_REGI_LOWER] ? a_i_reg[0:A_WIDTH/2-1] : a_i[0:A_WIDTH/2-1];
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assign in_a[A_WIDTH/2:A_WIDTH-1] = mode_i[MODE_BIT_REGI_UPPER] ? a_i_reg[A_WIDTH/2:A_WIDTH-1] : a_i[A_WIDTH/2:A_WIDTH-1];
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assign in_b[0:B_WIDTH/2-1] = mode_i[MODE_BIT_REGI_LOWER] ? b_i_reg[0:B_WIDTH/2-1] : b_i[0:B_WIDTH/2-1];
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assign in_b[B_WIDTH/2:B_WIDTH-1] = mode_i[MODE_BIT_REGI_UPPER] ? b_i_reg[B_WIDTH/2:B_WIDTH-1] : b_i[B_WIDTH/2:B_WIDTH-1];
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assign in_d[0:ACC_OUT_WIDTH/2-1] = mode_i[MODE_BIT_REGI_LOWER] ? d_i_reg[0:ACC_OUT_WIDTH/2-1] : d_i[0:ACC_OUT_WIDTH/2-1];
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assign in_d[ACC_OUT_WIDTH/2:ACC_OUT_WIDTH-1] = mode_i[MODE_BIT_REGI_UPPER] ? d_i_reg[ACC_OUT_WIDTH/2:ACC_OUT_WIDTH-1] : d_i[ACC_OUT_WIDTH/2:ACC_OUT_WIDTH-1];
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assign out_o[0:ACC_OUT_WIDTH/2-1] = mode_i[MODE_BIT_REGO_LOWER] ? out_o_reg[0:ACC_OUT_WIDTH/2-1] : cas_out[0:ACC_OUT_WIDTH/2-1];
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assign out_o[ACC_OUT_WIDTH/2:ACC_OUT_WIDTH-1] = mode_i[MODE_BIT_REGO_UPPER] ? out_o_reg[ACC_OUT_WIDTH/2:ACC_OUT_WIDTH-1] : cas_out[ACC_OUT_WIDTH/2:ACC_OUT_WIDTH-1];
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// Control logic for registering inputs and outputs of the multipliers
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wire [0:A_WIDTH-1] mac_a;
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wire [0:B_WIDTH-1] mac_b;
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wire [0:ACC_OUT_WIDTH-1] mac_d;
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wire [0:ACC_OUT_WIDTH-1] mac_out;
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reg [0:A_WIDTH-1] in_a_reg;
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reg [0:B_WIDTH-1] in_b_reg;
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reg [0:ACC_OUT_WIDTH-1] in_d_reg;
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wire [0:ACC_OUT_WIDTH/2-1] mul_out_0;
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wire [0:ACC_OUT_WIDTH/2-1] mul_out_1;
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wire [0:ACC_OUT_WIDTH/2-1] mul_out_2;
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wire [0:ACC_OUT_WIDTH/2-1] mul_out_3;
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reg [0:ACC_OUT_WIDTH/2-1] mul_out_0_reg;
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reg [0:ACC_OUT_WIDTH/2-1] mul_out_1_reg;
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reg [0:ACC_OUT_WIDTH/2-1] mul_out_2_reg;
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reg [0:ACC_OUT_WIDTH/2-1] mul_out_3_reg;
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wire [0:ACC_OUT_WIDTH/2-1] q_o_0;
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wire [0:ACC_OUT_WIDTH/2-1] q_o_1;
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wire [0:ACC_OUT_WIDTH/2-1] q_o_2;
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wire [0:ACC_OUT_WIDTH/2-1] q_o_3;
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always @(posedge clk_core or negedge clr) begin
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if (clr == 1'b0) begin
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in_a_reg <= 0;
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in_b_reg <= 0;
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in_d_reg <= 0;
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mul_out_0_reg <= 0;
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mul_out_1_reg <= 0;
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mul_out_2_reg <= 0;
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mul_out_3_reg <= 0;
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end else begin
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in_a_reg <= in_a;
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in_b_reg <= in_b;
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in_d_reg <= in_d;
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mul_out_0_reg <= mul_out_0;
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mul_out_1_reg <= mul_out_1;
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mul_out_2_reg <= mul_out_2;
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mul_out_3_reg <= mul_out_3;
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end
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end
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assign mac_a = mode_i[MODE_MUL_INPUT_REG] ? in_a_reg : in_a;
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assign mac_b = mode_i[MODE_MUL_INPUT_REG] ? in_b_reg : in_b;
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assign mac_d = mode_i[MODE_MUL_INPUT_REG] ? in_d_reg : in_d;
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assign q_o_0 = mode_i[MODE_MUL_OUTPUT_REG] ? mul_out_0_reg : mul_out_0;
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assign q_o_1 = mode_i[MODE_MUL_OUTPUT_REG] ? mul_out_1_reg : mul_out_1;
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assign q_o_2 = mode_i[MODE_MUL_OUTPUT_REG] ? mul_out_2_reg : mul_out_2;
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assign q_o_3 = mode_i[MODE_MUL_OUTPUT_REG] ? mul_out_3_reg : mul_out_3;
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// Control logic around the core computing units
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always @(*) begin
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case (mode_i[MODE_BIT_MAC_LSB:MODE_BIT_MAC_MSB])
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4'b0000: begin
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mul_out_0 = mac_a[0:A_WIDTH/4-1] * mac_b[0:B_WIDTH/4-1];
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mul_out_1 = mac_a[A_WIDTH/4:A_WIDTH/2-1] * mac_b[B_WIDTH/4:B_WIDTH/2-1] + q_o_0;
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mul_out_2 = mac_a[A_WIDTH/2:A_WIDTH/4*3-1] * mac_b[B_WIDTH/2:B_WIDTH/4*3-1] + q_o_1;
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mul_out_3 = mac_a[A_WIDTH/4*3:A_WIDTH-1] * mac_b[B_WIDTH/4*3:B_WIDTH-1] + q_o_2;
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mac_out = q_o_3;
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end
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4'b0001: begin
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mul_out_0 = mac_a[0:A_WIDTH/4-1] * mac_b[0:B_WIDTH/4-1] + mac_d[0:ACC_OUT_WIDTH/2-1];
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mul_out_2 = mac_a[A_WIDTH/2:A_WIDTH/4*3-1] * mac_b[B_WIDTH/2:B_WIDTH/4*3-1] + mac_d[ACC_OUT_WIDTH/2:ACC_OUT_WIDTH-1];
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mul_out_3 = mac_a[A_WIDTH/4*3:A_WIDTH-1] * mac_b[B_WIDTH/4*3:B_WIDTH-1] + q_o_2;
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mac_out = {q_o_0, q_o_3};
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end
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4'b0010: begin
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mul_out_0 = mac_a[0:A_WIDTH/4-1] * mac_b[0:B_WIDTH/4-1];
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mul_out_1 = mac_a[A_WIDTH/4:A_WIDTH/2-1] * mac_b[B_WIDTH/4:B_WIDTH/2-1] + q_o_0;
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mul_out_3 = mac_a[A_WIDTH/2:A_WIDTH/4*3-1] * mac_b[B_WIDTH/2:B_WIDTH/4*3-1];
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mac_out = {q_o_1, q_o_2};
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end
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4'b0011: begin
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mul_out_0 = mac_a[0:A_WIDTH/4-1] * mac_b[0:B_WIDTH/4-1] + out_o_reg[0:ACC_OUT_WIDTH/2-1];
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mul_out_1 = mac_a[A_WIDTH/4:A_WIDTH/2-1] * mac_b[B_WIDTH/4:B_WIDTH/2-1] + out_o_reg[ACC_OUT_WIDTH/2:ACC_OUT_WIDTH-1];
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mac_out = {q_o_0, q_o_1};
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end
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4'b0100: begin
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mac_out = mac_a[0:A_WIDTH/2-1] * mac_b[0:B_WIDTH/2-1];
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end
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4'b0101: begin
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mul_out_0 = mac_a[0:A_WIDTH/4-1] * mac_b[0:B_WIDTH/4-1] + mac_d[0:ACC_OUT_WIDTH/2-1];
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mul_out_1 = mac_a[A_WIDTH/4:A_WIDTH/2-1] * mac_b[B_WIDTH/4:B_WIDTH/2-1] + mac_d[ACC_OUT_WIDTH/2:ACC_OUT_WIDTH-1];
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mac_out = {q_o_0, q_o_1};
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end
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4'b0110: begin
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mul_out_0 = mac_a[0:A_WIDTH/4-1] * mac_b[0:B_WIDTH/4-1];
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mul_out_1 = mac_a[A_WIDTH/4:A_WIDTH/2-1] * mac_b[B_WIDTH/4:B_WIDTH/2-1];
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mul_out_2 = mac_a[A_WIDTH/2:A_WIDTH/4*3-1] * mac_b[B_WIDTH/2:B_WIDTH/4*3-1];
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mul_out_3 = mac_a[A_WIDTH/4*3:A_WIDTH-1] * mac_b[B_WIDTH/4*3:B_WIDTH-1];
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mac_out = {q_o_0[0:ACC_OUT_WIDTH/4-1], q_o_1[0:ACC_OUT_WIDTH/4-1], q_o_2[0:ACC_OUT_WIDTH/4-1], q_o_3[0:ACC_OUT_WIDTH/4-1]};
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end
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4'b1000: begin
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mul_out_0 = mac_a[0:A_WIDTH/4-1] * mac_b[0:B_WIDTH/4-1];
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mul_out_1 = mac_a[A_WIDTH/4:A_WIDTH/2-1] * mac_b[B_WIDTH/4:B_WIDTH/2-1];
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mac_out = {q_o_0, q_o_1};
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end
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4'b1001: begin
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mul_out_0 = mac_a[0:A_WIDTH/4-1] * mac_b[0:B_WIDTH/4-1] + mac_d[0:ACC_OUT_WIDTH/2-1];
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mul_out_1 = mac_a[A_WIDTH/4:A_WIDTH/2-1] * mac_b[B_WIDTH/4:B_WIDTH/2-1] + q_o_0;
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mul_out_2 = mac_a[A_WIDTH/2:A_WIDTH/4*3-1] * mac_b[B_WIDTH/2:B_WIDTH/4*3-1] + q_o_1;
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mul_out_3 = mac_a[A_WIDTH/4*3:A_WIDTH-1] * mac_b[B_WIDTH/4*3:B_WIDTH-1] + q_o_2;
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mac_out = {q_o_2, q_o_3};
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end
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4'b1010: begin
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mul_out_0 = mac_a[0:A_WIDTH/4-1] * mac_b[0:B_WIDTH/4-1];
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mul_out_1 = mac_a[A_WIDTH/4:A_WIDTH/2-1] * mac_b[B_WIDTH/4:B_WIDTH/2-1] + q_o_0;
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mul_out_2 = mac_a[A_WIDTH/2:A_WIDTH/4*3-1] * mac_b[B_WIDTH/2:B_WIDTH/4*3-1] + q_o_1;
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mul_out_3 = mac_a[A_WIDTH/4*3:A_WIDTH-1] * mac_b[B_WIDTH/4*3:B_WIDTH-1] + q_o_2;
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mac_out = {q_o_1, q_o_3};
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end
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4'b1011: begin
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mul_out_0 = mac_a[0:A_WIDTH/4-1] * mac_b[0:B_WIDTH/4-1];
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mul_out_1 = mac_a[A_WIDTH/4:A_WIDTH/2-1] * mac_b[B_WIDTH/4:B_WIDTH/2-1] + q_o_0;
|
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mul_out_2 = mac_a[A_WIDTH/2:A_WIDTH/4*3-1] * mac_b[B_WIDTH/2:B_WIDTH/4*3-1];
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mul_out_3 = mac_a[A_WIDTH/4*3:A_WIDTH-1] * mac_b[B_WIDTH/4*3:B_WIDTH-1] + q_o_2;
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mac_out = {q_o_1, q_o_3};
|
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end
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4'b1101: begin
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mul_out_2 = mac_a[A_WIDTH/2:A_WIDTH/4*3-1] * mac_b[B_WIDTH/2:B_WIDTH/4*3-1] + mac_d[0:ACC_OUT_WIDTH/2-1];
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mul_out_3 = mac_a[A_WIDTH/4*3:A_WIDTH-1] * mac_b[B_WIDTH/4*3:B_WIDTH-1] + mac_d[ACC_OUT_WIDTH/2:ACC_OUT_WIDTH-1];
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mac_out = {q_o_2, q_o_3};
|
|
end
|
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4'b1110: begin
|
|
mul_out_0 = mac_a[0:A_WIDTH/4-1] * mac_b[0:B_WIDTH/4-1];
|
|
mul_out_2 = mac_a[A_WIDTH/2:A_WIDTH/4*3-1] * mac_b[B_WIDTH/2:B_WIDTH/4*3-1];
|
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mul_out_3 = mac_a[A_WIDTH/4*3:A_WIDTH-1] * mac_b[B_WIDTH/4*3:B_WIDTH-1];
|
|
mac_out = {q_o_0, q_o_2[0:ACC_OUT_WIDTH/4-1], q_o_3[0:ACC_OUT_WIDTH/4-1]};
|
|
end
|
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default: begin
|
|
mul_out_0 = mac_a[0:A_WIDTH/4-1] * mac_b[0:B_WIDTH/4-1];
|
|
mul_out_2 = mac_a[A_WIDTH/2:A_WIDTH/4*3-1] * mac_b[B_WIDTH/2:B_WIDTH/4*3-1];
|
|
mul_out_3 = mac_a[A_WIDTH/4*3:A_WIDTH-1] * mac_b[B_WIDTH/4*3:B_WIDTH-1];
|
|
mac_out = {q_o_0, q_o_2[0:ACC_OUT_WIDTH/4-1], q_o_3[0:ACC_OUT_WIDTH/4-1]};
|
|
end
|
|
endcase
|
|
end
|
|
|
|
always @(*) begin
|
|
cas_out = cas_g ? mac_out + mac_d : mac_out;
|
|
end
|
|
|
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endmodule |