mirror of https://github.com/YosysHQ/yosys.git
55 lines
1.3 KiB
Plaintext
55 lines
1.3 KiB
Plaintext
pattern sub2neg
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//
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// Authored by Abhinav Tondapu of Silimate, Inc. under ISC license.
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//
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// Convert subtraction to addition with negation
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//
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// a - b ===> a + (-b)
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//
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state <SigSpec> sub_a sub_b sub_y
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state <bool> a_signed b_signed
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match sub
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select sub->type == $sub
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filter !sub->getPort(\B).is_fully_const()
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set sub_a port(sub, \A)
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set sub_b port(sub, \B)
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set sub_y port(sub, \Y)
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set a_signed sub->getParam(\A_SIGNED).as_bool()
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set b_signed sub->getParam(\B_SIGNED).as_bool()
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endmatch
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code sub_a sub_b sub_y a_signed b_signed
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if (a_signed != b_signed)
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reject;
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{
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int width = GetSize(sub_y);
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Cell *cell = sub;
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SigSpec sub_a_rs = sub_a;
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SigSpec sub_b_rs = sub_b;
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// Anchor operands to the original subtract width to preserve wrap behavior
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sub_a_rs.extend_u0(width, a_signed);
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sub_b_rs.extend_u0(width, b_signed);
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// Negate within the anchored width, then reuse the original cell as $add
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SigSpec neg_y = module->addWire(NEW_ID2_SUFFIX("neg_y"), width);
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Cell *neg = module->addNeg(NEW_ID2_SUFFIX("neg"), sub_b_rs, neg_y, b_signed);
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sub->setPort(\A, sub_a_rs);
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sub->setPort(\B, neg_y);
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sub->setPort(\Y, sub_y);
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sub->type = $add;
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log(" sub=%s -> neg=%s, add=%s\n",
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log_id(sub), log_id(neg), log_id(sub));
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sub->fixup_parameters();
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neg->fixup_parameters();
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did_something = true;
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}
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accept;
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endcode
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