mirror of https://github.com/YosysHQ/yosys.git
76 lines
1.8 KiB
Plaintext
76 lines
1.8 KiB
Plaintext
pattern expand
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//
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// Authored by Akash Levy of Silimate, Inc. under ISC license.
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//
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// Expand logical conjunction (&) across (|)
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//
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// y = (a | b) & c ===> y = (a & c) | (b & c)
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//
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state <SigSpec> and_a and_b and_y or_a or_b or_y
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match or_gate
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// Select OR gate
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select or_gate->type.in($or, $_OR_)
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set or_a port(or_gate, \A)
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set or_b port(or_gate, \B)
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set or_y port(or_gate, \Y)
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endmatch
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code
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// Fanout of each OR gate Y bit should be 1 (no bit-split)
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if (nusers(or_y) != 2)
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reject;
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endcode
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match and_gate
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// Select AND gate
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select and_gate->type.in($and, $_AND_)
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// Set ports, allowing A and B to be swapped
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choice <IdString> A {\A, \B}
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define <IdString> B (A == \A ? \B : \A)
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set and_a port(and_gate, A)
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set and_b port(and_gate, B)
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set and_y port(and_gate, \Y)
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// Connection
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index <SigSpec> port(and_gate, A) === or_y
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endmatch
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code and_a and_b and_y or_a or_b or_y
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// Unset all ports
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and_gate->unsetPort(\A);
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and_gate->unsetPort(\B);
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and_gate->unsetPort(\Y);
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or_gate->unsetPort(\A);
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or_gate->unsetPort(\B);
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or_gate->unsetPort(\Y);
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// Create new intermediate wires
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Cell *cell = and_gate;
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Wire *new_or_a = module->addWire(NEW_ID2, GetSize(and_y));
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Wire *new_or_b = module->addWire(NEW_ID2, GetSize(and_y));
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// Create new AND gates connected to the OR gate
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module->addAnd(NEW_ID2, or_a, and_b, new_or_a, false, cell->get_src_attribute());
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module->addAnd(NEW_ID2, or_b, and_b, new_or_b, false, cell->get_src_attribute());
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// Update OR gate ports
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or_gate->setPort(\A, new_or_a);
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or_gate->setPort(\B, new_or_b);
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or_gate->setPort(\Y, and_y);
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// Rename OR gate for formal
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cell = or_gate;
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module->rename(or_gate, NEW_ID2);
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// Remove AND gate
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autoremove(and_gate);
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// Log, fixup, accept
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log("expand pattern in %s: and=%s, or=%s\n", log_id(module), log_id(and_gate), log_id(or_gate));
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did_something = true;
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accept;
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endcode
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