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mirror of https://github.com/YosysHQ/yosys.git synced 2026-09-02 02:57:40 +02:00
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2858bb03cd1e3417a5a8c4ebca10877b4fd64bfa
yosys/tests/proc
T
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Marcelina Kościelnicka 990c9b8e11 Add proc_rom pass.
2022-05-13 00:37:14 +02:00
..
.gitignore
proc_clean: fix order of switch insertion.
2019-08-19 16:44:23 +00:00
bug2619.ys
proc_dff: Fix emitted FF when a register is not assigned in async reset
2021-03-08 17:01:43 +01:00
bug2656.ys
proc_arst: Add special-casing of clock signal in conditionals.
2021-03-15 17:17:29 +01:00
bug2962.ys
proc_prune: Make assign removal and promotion per-bit, remember promoted bits.
2021-08-14 15:26:11 +02:00
bug_1268.v
proc_clean: fix order of switch insertion.
2019-08-19 16:44:23 +00:00
bug_1268.ys
proc_clean: fix order of switch insertion.
2019-08-19 16:44:23 +00:00
proc_rom.ys
Add proc_rom pass.
2022-05-13 00:37:14 +02:00
rmdead.v
proc_rmdead: use explicit pattern set when there are no wildcards
2021-07-29 20:55:59 -04:00
rmdead.ys
proc_rmdead: use explicit pattern set when there are no wildcards
2021-07-29 20:55:59 -04:00
run-test.sh
proc_clean: fix order of switch insertion.
2019-08-19 16:44:23 +00:00
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